Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9791965 9790745 0 0
selKnown1 71409644 71408424 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9791965 9790745 0 0
T1 34060 34056 0 0
T2 83853 83849 0 0
T3 218 214 0 0
T4 0 8 0 0
T7 4400 4396 0 0
T8 19960 19956 0 0
T9 18618 18614 0 0
T13 21520 21516 0 0
T15 16048 16044 0 0
T16 511956 511952 0 0
T18 0 12 0 0
T23 222 218 0 0
T49 0 12 0 0
T59 0 8 0 0
T70 0 12 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 71409644 71408424 0 0
T1 920093 920089 0 0
T2 258792 258788 0 0
T3 2545 2541 0 0
T4 0 6 0 0
T7 17143 17139 0 0
T8 115736 115732 0 0
T9 120238 120234 0 0
T13 92594 92590 0 0
T15 44886 44882 0 0
T16 923792 923789 0 0
T18 0 12 0 0
T20 0 8 0 0
T23 2282 2278 0 0
T49 0 12 0 0
T59 0 8 0 0
T70 0 12 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 3005501 3005304 0 0
selKnown1 64623419 64623222 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 3005501 3005304 0 0
T1 17025 17024 0 0
T2 41916 41915 0 0
T3 108 107 0 0
T7 2195 2194 0 0
T8 9979 9978 0 0
T9 9308 9307 0 0
T13 10759 10758 0 0
T15 8020 8019 0 0
T16 255972 255971 0 0
T23 110 109 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 64623419 64623222 0 0
T1 903058 903057 0 0
T2 216872 216871 0 0
T3 2435 2434 0 0
T7 14946 14945 0 0
T8 105755 105754 0 0
T9 110928 110927 0 0
T13 81833 81832 0 0
T15 36858 36857 0 0
T16 667808 667808 0 0
T23 2170 2169 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 571 374 0 0
selKnown1 518 321 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 571 374 0 0
T1 5 4 0 0
T2 6 5 0 0
T3 1 0 0 0
T4 0 3 0 0
T7 5 4 0 0
T8 1 0 0 0
T9 1 0 0 0
T13 1 0 0 0
T15 4 3 0 0
T16 6 5 0 0
T18 0 6 0 0
T23 1 0 0 0
T49 0 6 0 0
T59 0 4 0 0
T70 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 518 321 0 0
T1 5 4 0 0
T2 2 1 0 0
T3 1 0 0 0
T4 0 3 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 1 0 0 0
T13 1 0 0 0
T15 4 3 0 0
T16 6 5 0 0
T18 0 6 0 0
T20 0 4 0 0
T23 1 0 0 0
T49 0 6 0 0
T59 0 4 0 0
T70 0 6 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6784081 6783668 0 0
selKnown1 6784081 6783668 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6784081 6783668 0 0
T1 17025 17024 0 0
T2 41916 41915 0 0
T3 108 107 0 0
T7 2195 2194 0 0
T8 9979 9978 0 0
T9 9308 9307 0 0
T13 10759 10758 0 0
T15 8020 8019 0 0
T16 255972 255971 0 0
T23 110 109 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6784081 6783668 0 0
T1 17025 17024 0 0
T2 41916 41915 0 0
T3 108 107 0 0
T7 2195 2194 0 0
T8 9979 9978 0 0
T9 9308 9307 0 0
T13 10759 10758 0 0
T15 8020 8019 0 0
T16 255972 255971 0 0
T23 110 109 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1812 1399 0 0
selKnown1 1626 1213 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1812 1399 0 0
T1 5 4 0 0
T2 15 14 0 0
T3 1 0 0 0
T4 0 5 0 0
T7 5 4 0 0
T8 1 0 0 0
T9 1 0 0 0
T13 1 0 0 0
T15 4 3 0 0
T16 6 5 0 0
T18 0 6 0 0
T23 1 0 0 0
T49 0 6 0 0
T59 0 4 0 0
T70 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1626 1213 0 0
T1 5 4 0 0
T2 2 1 0 0
T3 1 0 0 0
T4 0 3 0 0
T7 1 0 0 0
T8 1 0 0 0
T9 1 0 0 0
T13 1 0 0 0
T15 4 3 0 0
T16 6 5 0 0
T18 0 6 0 0
T20 0 4 0 0
T23 1 0 0 0
T49 0 6 0 0
T59 0 4 0 0
T70 0 6 0 0

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