Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	238805	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	632688	1		T1	6		T9	1		T10	9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	550604	1		T1	6		T6	10		T11	6
values[0x0]	156832	1		T1	7		T9	4		T10	17
values[0x1]	164057	1		T1	10		T9	6		T10	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	181490	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	690003	1		T1	9		T9	2		T10	12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2966	1		T22	1		T136	1		T61	158
valid_sources[0x01]	3407	1		T23	1		T41	1		T61	138
valid_sources[0x02]	3324	1		T13	1		T41	1		T40	1
valid_sources[0x03]	3306	1		T16	1		T22	1		T40	2
valid_sources[0x04]	3378	1		T22	2		T137	7		T61	136
valid_sources[0x05]	2929	1		T22	2		T41	1		T61	144
valid_sources[0x06]	3412	1		T10	10		T21	2		T46	1
valid_sources[0x07]	3499	1		T41	1		T61	145		T59	9
valid_sources[0x08]	2989	1		T8	1		T24	1		T40	2
valid_sources[0x09]	3963	1		T61	133		T55	49		T56	1
valid_sources[0x0a]	3285	1		T7	1		T23	1		T61	161
valid_sources[0x0b]	3060	1		T24	2		T22	3		T41	2
valid_sources[0x0c]	3095	1		T61	122		T55	41		T56	5
valid_sources[0x0d]	3418	1		T23	1		T41	2		T61	137
valid_sources[0x0e]	3153	1		T24	1		T23	1		T61	125
valid_sources[0x0f]	3297	1		T8	2		T138	4		T22	2
valid_sources[0x10]	3158	1		T22	1		T23	2		T41	1
valid_sources[0x11]	2993	1		T47	1		T61	140		T59	19
valid_sources[0x12]	3539	1		T21	1		T23	1		T61	130
valid_sources[0x13]	3306	1		T13	2		T40	4		T61	137
valid_sources[0x14]	3093	1		T61	139		T59	4		T55	42
valid_sources[0x15]	4238	1		T61	136		T59	16		T55	32
valid_sources[0x16]	3404	1		T139	1		T61	136		T59	11
valid_sources[0x17]	3034	1		T23	1		T40	1		T140	1
valid_sources[0x18]	3803	1		T138	2		T40	1		T61	134
valid_sources[0x19]	3199	1		T61	117		T59	3		T55	33
valid_sources[0x1a]	3826	1		T1	1		T6	1		T23	1
valid_sources[0x1b]	3291	1		T41	3		T47	1		T61	158
valid_sources[0x1c]	3084	1		T9	10		T22	1		T61	124
valid_sources[0x1d]	3128	1		T10	4		T6	1		T11	14
valid_sources[0x1e]	3380	1		T13	1		T61	135		T59	2
valid_sources[0x1f]	3354	1		T1	1		T8	1		T23	1
valid_sources[0x20]	3299	1		T22	1		T23	1		T61	124
valid_sources[0x21]	3115	1		T41	1		T47	1		T61	142
valid_sources[0x22]	3091	1		T8	2		T41	1		T61	160
valid_sources[0x23]	3292	1		T61	110		T59	2		T55	34
valid_sources[0x24]	2998	1		T61	112		T55	37		T58	2
valid_sources[0x25]	3699	1		T24	1		T41	2		T40	2
valid_sources[0x26]	4092	1		T40	1		T61	141		T59	12
valid_sources[0x27]	3111	1		T8	1		T61	152		T59	1
valid_sources[0x28]	4358	1		T13	3		T41	1		T61	105
valid_sources[0x29]	3124	1		T38	80		T22	1		T61	139
valid_sources[0x2a]	4018	1		T24	1		T61	122		T55	47
valid_sources[0x2b]	3154	1		T22	1		T141	15		T61	150
valid_sources[0x2c]	3117	1		T22	1		T23	1		T61	136
valid_sources[0x2d]	3410	1		T7	1		T23	1		T40	1
valid_sources[0x2e]	3004	1		T41	1		T61	133		T55	33
valid_sources[0x2f]	3501	1		T41	1		T61	128		T55	33
valid_sources[0x30]	3113	1		T6	1		T8	2		T24	3
valid_sources[0x31]	3684	1		T7	1		T41	1		T40	2
valid_sources[0x32]	3023	1		T1	1		T41	2		T61	128
valid_sources[0x33]	2925	1		T41	1		T61	129		T59	11
valid_sources[0x34]	3369	1		T22	1		T23	1		T61	95
valid_sources[0x35]	3092	1		T13	1		T22	1		T61	125
valid_sources[0x36]	3298	1		T61	159		T59	1		T55	29
valid_sources[0x37]	3660	1		T138	1		T28	1		T40	2
valid_sources[0x38]	3600	1		T8	1		T41	2		T61	124
valid_sources[0x39]	3534	1		T6	2		T41	1		T61	156
valid_sources[0x3a]	3780	1		T22	1		T46	1		T23	1
valid_sources[0x3b]	5122	1		T22	1		T61	126		T55	38
valid_sources[0x3c]	3040	1		T7	1		T41	2		T61	140
valid_sources[0x3d]	4340	1		T21	3		T41	1		T61	133
valid_sources[0x3e]	3175	1		T23	1		T141	2		T40	2
valid_sources[0x3f]	3355	1		T8	1		T22	1		T137	5
valid_sources[0x40]	2888	1		T40	1		T61	138		T59	1
valid_sources[0x41]	3678	1		T139	3		T41	1		T47	1
valid_sources[0x42]	3214	1		T61	135		T59	9		T55	39
valid_sources[0x43]	4153	1		T8	3		T61	136		T59	10
valid_sources[0x44]	3409	1		T13	1		T43	14		T23	1
valid_sources[0x45]	3942	1		T136	1		T47	1		T40	1
valid_sources[0x46]	3276	1		T139	2		T41	3		T40	4
valid_sources[0x47]	11033	1		T61	127		T59	1		T55	38
valid_sources[0x48]	3273	1		T22	1		T23	1		T40	3
valid_sources[0x49]	3673	1		T139	4		T41	1		T61	137
valid_sources[0x4a]	3335	1		T23	3		T41	1		T40	1
valid_sources[0x4b]	3248	1		T41	3		T61	120		T55	39
valid_sources[0x4c]	5101	1		T41	4		T61	129		T59	5
valid_sources[0x4d]	3270	1		T45	9		T22	1		T141	9
valid_sources[0x4e]	3117	1		T7	1		T8	2		T141	10
valid_sources[0x4f]	3334	1		T8	1		T22	1		T136	1
valid_sources[0x50]	3106	1		T61	131		T59	11		T55	34
valid_sources[0x51]	3302	1		T61	134		T59	9		T55	44
valid_sources[0x52]	3299	1		T22	1		T139	1		T137	2
valid_sources[0x53]	3261	1		T23	2		T40	1		T61	119
valid_sources[0x54]	3015	1		T1	3		T24	1		T22	1
valid_sources[0x55]	3054	1		T8	1		T40	1		T61	138
valid_sources[0x56]	3485	1		T61	141		T59	13		T55	39
valid_sources[0x57]	2853	1		T142	17		T61	111		T55	28
valid_sources[0x58]	3279	1		T41	1		T61	121		T59	7
valid_sources[0x59]	3086	1		T8	2		T61	126		T59	21
valid_sources[0x5a]	3622	1		T13	3		T61	147		T59	12
valid_sources[0x5b]	3461	1		T13	2		T61	156		T59	4
valid_sources[0x5c]	3400	1		T16	3		T41	1		T61	142
valid_sources[0x5d]	2980	1		T61	137		T59	2		T55	46
valid_sources[0x5e]	3440	1		T22	1		T61	117		T59	2
valid_sources[0x5f]	3044	1		T8	2		T40	3		T61	129
valid_sources[0x60]	3398	1		T61	136		T55	55		T57	1
valid_sources[0x61]	3197	1		T8	1		T61	142		T59	17
valid_sources[0x62]	2978	1		T42	12		T61	125		T59	4
valid_sources[0x63]	3310	1		T21	1		T17	1		T61	110
valid_sources[0x64]	3323	1		T23	1		T41	1		T40	1
valid_sources[0x65]	3180	1		T23	1		T40	1		T61	110
valid_sources[0x66]	3213	1		T22	1		T136	1		T41	1
valid_sources[0x67]	8724	1		T22	1		T40	1		T61	187
valid_sources[0x68]	3400	1		T6	1		T21	2		T23	1
valid_sources[0x69]	3105	1		T23	1		T136	1		T41	1
valid_sources[0x6a]	3006	1		T1	2		T40	3		T61	153
valid_sources[0x6b]	3076	1		T6	1		T24	1		T22	1
valid_sources[0x6c]	3154	1		T23	1		T41	1		T61	123
valid_sources[0x6d]	3551	1		T22	1		T61	131		T59	4
valid_sources[0x6e]	3308	1		T22	1		T23	3		T41	1
valid_sources[0x6f]	3562	1		T7	4		T61	134		T55	39
valid_sources[0x70]	3452	1		T61	126		T55	41		T51	2
valid_sources[0x71]	3057	1		T41	1		T61	135		T59	20
valid_sources[0x72]	3301	1		T61	126		T59	8		T55	37
valid_sources[0x73]	3441	1		T13	3		T23	1		T41	2
valid_sources[0x74]	3686	1		T8	2		T23	1		T61	137
valid_sources[0x75]	4533	1		T8	1		T24	1		T61	122
valid_sources[0x76]	3099	1		T41	1		T61	106		T59	1
valid_sources[0x77]	2849	1		T8	1		T22	1		T61	150
valid_sources[0x78]	3259	1		T61	117		T55	41		T58	1
valid_sources[0x79]	3195	1		T1	3		T61	126		T59	3
valid_sources[0x7a]	3797	1		T41	2		T143	1		T61	144
valid_sources[0x7b]	3315	1		T13	2		T23	2		T61	121
valid_sources[0x7c]	3759	1		T13	2		T22	1		T40	4
valid_sources[0x7d]	3385	1		T23	1		T61	132		T59	2
valid_sources[0x7e]	3310	1		T41	1		T40	2		T61	137
valid_sources[0x7f]	3156	1		T46	2		T61	126		T59	1
valid_sources[0x80]	3072	1		T46	1		T23	1		T41	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

322837

1

T1

2

T6

7

T11

4

values[0x0]

all_enables

biggest_size

154671

1

T1

1

T9

1

T10

5

values[0x1]

all_enables

biggest_size

155180

1

T1

3

T10

4

T13

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5257	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	21968	1		T2	4		T4	1		T31	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10257	1		T61	192		T59	6		T55	67
values[0x0]	8388	1		T2	11		T4	10		T31	7
values[0x1]	8580	1		T2	8		T4	9		T31	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3963	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	23262	1		T2	6		T4	3		T31	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	82	1		T118	1		T144	10		T58	1
valid_sources[0x01]	72	1		T145	1		T58	1		T88	1
valid_sources[0x02]	73	1		T57	1		T58	2		T75	1
valid_sources[0x03]	197	1		T146	1		T57	1		T51	125
valid_sources[0x04]	204	1		T58	2		T75	1		T83	2
valid_sources[0x05]	172	1		T75	1		T88	2		T78	1
valid_sources[0x06]	90	1		T75	1		T89	1		T147	1
valid_sources[0x07]	89	1		T57	1		T75	1		T78	2
valid_sources[0x08]	75	1		T118	2		T57	1		T75	1
valid_sources[0x09]	74	1		T148	8		T57	1		T75	1
valid_sources[0x0a]	103	1		T149	1		T57	2		T75	1
valid_sources[0x0b]	91	1		T60	1		T83	1		T78	1
valid_sources[0x0c]	94	1		T120	1		T58	1		T76	23
valid_sources[0x0d]	82	1		T150	1		T146	3		T57	1
valid_sources[0x0e]	181	1		T151	1		T58	2		T76	4
valid_sources[0x0f]	57	1		T78	3		T127	8		T89	4
valid_sources[0x10]	223	1		T152	3		T57	2		T78	1
valid_sources[0x11]	86	1		T119	4		T146	1		T51	1
valid_sources[0x12]	77	1		T55	3		T76	5		T78	1
valid_sources[0x13]	164	1		T75	1		T88	2		T78	4
valid_sources[0x14]	194	1		T76	6		T78	1		T89	9
valid_sources[0x15]	71	1		T153	2		T154	1		T155	2
valid_sources[0x16]	189	1		T150	1		T120	2		T156	2
valid_sources[0x17]	66	1		T157	1		T154	1		T75	1
valid_sources[0x18]	202	1		T78	4		T127	1		T147	1
valid_sources[0x19]	57	1		T154	1		T57	1		T75	2
valid_sources[0x1a]	53	1		T57	2		T75	3		T76	4
valid_sources[0x1b]	89	1		T158	1		T75	2		T78	3
valid_sources[0x1c]	159	1		T150	2		T58	1		T75	1
valid_sources[0x1d]	86	1		T57	2		T76	6		T78	8
valid_sources[0x1e]	70	1		T74	2		T159	1		T57	1
valid_sources[0x1f]	97	1		T60	1		T75	3		T77	3
valid_sources[0x20]	52	1		T75	1		T88	1		T78	5
valid_sources[0x21]	65	1		T62	1		T160	1		T154	1
valid_sources[0x22]	71	1		T75	2		T83	2		T78	3
valid_sources[0x23]	84	1		T146	2		T55	3		T57	2
valid_sources[0x24]	83	1		T150	1		T57	1		T76	3
valid_sources[0x25]	71	1		T155	6		T58	2		T75	2
valid_sources[0x26]	88	1		T2	1		T58	1		T51	1
valid_sources[0x27]	94	1		T74	1		T157	1		T58	1
valid_sources[0x28]	106	1		T150	1		T146	1		T55	3
valid_sources[0x29]	174	1		T57	1		T127	3		T113	1
valid_sources[0x2a]	175	1		T161	3		T75	2		T88	1
valid_sources[0x2b]	83	1		T121	1		T76	3		T78	2
valid_sources[0x2c]	92	1		T57	2		T78	1		T89	1
valid_sources[0x2d]	184	1		T62	1		T150	1		T76	8
valid_sources[0x2e]	66	1		T76	3		T89	2		T99	5
valid_sources[0x2f]	108	1		T157	1		T161	1		T78	3
valid_sources[0x30]	103	1		T150	1		T57	1		T75	1
valid_sources[0x31]	168	1		T55	3		T51	7		T78	4
valid_sources[0x32]	144	1		T120	2		T57	1		T75	1
valid_sources[0x33]	75	1		T118	3		T57	1		T75	1
valid_sources[0x34]	73	1		T146	1		T78	7		T162	1
valid_sources[0x35]	94	1		T4	19		T154	1		T76	4
valid_sources[0x36]	151	1		T120	1		T88	2		T83	1
valid_sources[0x37]	74	1		T58	2		T83	1		T78	1
valid_sources[0x38]	69	1		T163	1		T57	1		T76	2
valid_sources[0x39]	49	1		T54	1		T156	1		T57	1
valid_sources[0x3a]	93	1		T151	1		T57	3		T77	3
valid_sources[0x3b]	103	1		T156	4		T57	1		T58	2
valid_sources[0x3c]	126	1		T58	2		T75	1		T81	2
valid_sources[0x3d]	77	1		T62	1		T74	1		T57	1
valid_sources[0x3e]	90	1		T74	1		T161	4		T154	1
valid_sources[0x3f]	70	1		T57	1		T58	1		T75	1
valid_sources[0x40]	75	1		T163	1		T78	2		T79	3
valid_sources[0x41]	116	1		T151	1		T55	3		T78	2
valid_sources[0x42]	98	1		T146	1		T57	2		T77	24
valid_sources[0x43]	54	1		T161	1		T88	3		T89	2
valid_sources[0x44]	90	1		T154	2		T57	2		T75	2
valid_sources[0x45]	81	1		T31	1		T145	2		T58	1
valid_sources[0x46]	69	1		T164	1		T75	1		T78	4
valid_sources[0x47]	101	1		T33	14		T57	1		T58	1
valid_sources[0x48]	86	1		T55	7		T56	1		T76	1
valid_sources[0x49]	63	1		T54	1		T163	1		T57	1
valid_sources[0x4a]	95	1		T57	1		T58	1		T75	1
valid_sources[0x4b]	91	1		T148	1		T153	1		T159	2
valid_sources[0x4c]	88	1		T78	1		T89	2		T165	1
valid_sources[0x4d]	93	1		T154	1		T60	1		T58	1
valid_sources[0x4e]	81	1		T158	1		T146	1		T161	1
valid_sources[0x4f]	79	1		T88	1		T77	2		T78	1
valid_sources[0x50]	226	1		T166	4		T78	1		T127	1
valid_sources[0x51]	306	1		T2	1		T153	2		T57	1
valid_sources[0x52]	119	1		T75	1		T78	7		T89	3
valid_sources[0x53]	137	1		T31	1		T54	2		T76	3
valid_sources[0x54]	49	1		T75	1		T78	1		T162	2
valid_sources[0x55]	108	1		T62	1		T120	2		T51	38
valid_sources[0x56]	63	1		T58	1		T75	1		T78	2
valid_sources[0x57]	125	1		T2	4		T59	1		T76	6
valid_sources[0x58]	92	1		T57	2		T58	3		T75	1
valid_sources[0x59]	175	1		T161	1		T57	1		T76	18
valid_sources[0x5a]	83	1		T72	2		T57	1		T56	20
valid_sources[0x5b]	87	1		T73	3		T55	6		T58	1
valid_sources[0x5c]	117	1		T31	1		T75	1		T76	1
valid_sources[0x5d]	85	1		T78	6		T79	9		T127	8
valid_sources[0x5e]	188	1		T57	1		T75	1		T88	1
valid_sources[0x5f]	84	1		T58	3		T51	1		T78	1
valid_sources[0x60]	80	1		T74	1		T158	1		T55	3
valid_sources[0x61]	108	1		T55	10		T58	1		T76	2
valid_sources[0x62]	87	1		T55	3		T57	2		T58	1
valid_sources[0x63]	118	1		T78	4		T89	1		T147	2
valid_sources[0x64]	79	1		T2	1		T78	3		T89	2
valid_sources[0x65]	68	1		T75	2		T77	1		T78	4
valid_sources[0x66]	87	1		T54	1		T57	1		T58	1
valid_sources[0x67]	95	1		T167	4		T156	1		T163	1
valid_sources[0x68]	152	1		T78	2		T89	1		T147	1
valid_sources[0x69]	82	1		T2	1		T154	1		T57	2
valid_sources[0x6a]	83	1		T168	2		T153	1		T60	1
valid_sources[0x6b]	64	1		T62	1		T168	1		T157	2
valid_sources[0x6c]	55	1		T88	6		T78	4		T99	4
valid_sources[0x6d]	60	1		T57	1		T75	4		T78	1
valid_sources[0x6e]	82	1		T146	1		T75	1		T88	2
valid_sources[0x6f]	83	1		T74	1		T55	7		T78	1
valid_sources[0x70]	69	1		T32	1		T156	1		T57	1
valid_sources[0x71]	67	1		T169	6		T57	1		T76	7
valid_sources[0x72]	159	1		T32	4		T160	1		T58	1
valid_sources[0x73]	66	1		T150	1		T77	1		T78	4
valid_sources[0x74]	105	1		T152	4		T57	1		T60	3
valid_sources[0x75]	78	1		T58	1		T78	1		T99	2
valid_sources[0x76]	148	1		T55	3		T58	3		T51	67
valid_sources[0x77]	46	1		T59	7		T57	2		T58	1
valid_sources[0x78]	66	1		T118	1		T78	4		T89	1
valid_sources[0x79]	89	1		T55	19		T57	1		T78	3
valid_sources[0x7a]	884	1		T2	1		T170	1		T55	10
valid_sources[0x7b]	85	1		T72	1		T89	3		T147	2
valid_sources[0x7c]	62	1		T166	1		T75	3		T89	4
valid_sources[0x7d]	105	1		T121	2		T146	1		T153	1
valid_sources[0x7e]	82	1		T74	1		T158	1		T163	1
valid_sources[0x7f]	79	1		T62	1		T150	1		T58	1
valid_sources[0x80]	147	1		T74	2		T55	18		T56	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7245

1

T61

97

T59

3

T55

21

values[0x0]

all_enables

biggest_size

7532

1

T2

2

T4

1

T31

2

values[0x1]

all_enables

biggest_size

7191

1

T2

2

T31

1

T32

1