SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 901604 | 1 | T1 | 23 | T9 | 10 | T10 | 36 | |||
auto[1] | 24474 | 1 | T38 | 80 | T39 | 80 | T55 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 925880 | 1 | T1 | 23 | T9 | 10 | T10 | 36 | |||
values[1] | 16 | 1 | T75 | 2 | T88 | 1 | T77 | 2 | |||
values[2] | 3 | 1 | T79 | 1 | T124 | 1 | T126 | 1 | |||
values[3] | 105 | 1 | T55 | 5 | T75 | 5 | T88 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 925881 | 1 | T1 | 23 | T9 | 10 | T10 | 36 | |||
values[1] | 14 | 1 | T55 | 2 | T75 | 2 | T88 | 1 | |||
values[2] | 4 | 1 | T127 | 1 | T124 | 1 | T128 | 2 | |||
values[3] | 100 | 1 | T55 | 10 | T75 | 5 | T88 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 925778 | 1 | T1 | 23 | T9 | 10 | T10 | 36 | |||
auto[TlIntgErrCmd] | 103 | 1 | T55 | 6 | T75 | 8 | T88 | 4 | |||
auto[TlIntgErrData] | 102 | 1 | T55 | 7 | T75 | 9 | T88 | 8 | |||
auto[TlIntgErrBoth] | 95 | 1 | T55 | 7 | T75 | 3 | T88 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 49246 | 0 | T2 | 19 | T4 | 19 | T31 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 49038 | 1 | T2 | 19 | T4 | 19 | T31 | 11 | |||
values[1] | 29 | 1 | T55 | 2 | T75 | 1 | T88 | 1 | |||
values[2] | 5 | 1 | T88 | 1 | T129 | 1 | T130 | 1 | |||
values[3] | 107 | 1 | T55 | 6 | T75 | 8 | T88 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 49047 | 1 | T2 | 19 | T4 | 19 | T31 | 11 | |||
values[1] | 14 | 1 | T55 | 2 | T75 | 3 | T127 | 1 | |||
values[2] | 6 | 1 | T88 | 3 | T77 | 1 | T131 | 1 | |||
values[3] | 101 | 1 | T55 | 1 | T75 | 8 | T88 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 48946 | 1 | T2 | 19 | T4 | 19 | T31 | 11 | |||
auto[TlIntgErrCmd] | 101 | 1 | T55 | 9 | T75 | 3 | T88 | 6 | |||
auto[TlIntgErrData] | 92 | 1 | T55 | 6 | T75 | 6 | T88 | 6 | |||
auto[TlIntgErrBoth] | 107 | 1 | T55 | 5 | T75 | 11 | T88 | 8 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |