Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
291319 |
1 |
|
T1 |
17 |
|
T9 |
9 |
|
T10 |
27 |
full_word |
634759 |
1 |
|
T1 |
6 |
|
T9 |
1 |
|
T10 |
9 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
925778 |
1 |
|
T1 |
23 |
|
T9 |
10 |
|
T10 |
36 |
auto[TlIntgErrCmd] |
103 |
1 |
|
T55 |
6 |
|
T75 |
8 |
|
T88 |
4 |
auto[TlIntgErrData] |
102 |
1 |
|
T55 |
7 |
|
T75 |
9 |
|
T88 |
8 |
auto[TlIntgErrBoth] |
95 |
1 |
|
T55 |
7 |
|
T75 |
3 |
|
T88 |
8 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
553087 |
1 |
|
T1 |
6 |
|
T6 |
10 |
|
T11 |
6 |
auto[1] |
372991 |
1 |
|
T1 |
17 |
|
T9 |
10 |
|
T10 |
36 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
229873 |
1 |
|
T1 |
4 |
|
T6 |
3 |
|
T11 |
2 |
auto[TlIntgErrNone] |
partial |
auto[1] |
61178 |
1 |
|
T1 |
13 |
|
T9 |
9 |
|
T10 |
27 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
323083 |
1 |
|
T1 |
2 |
|
T6 |
7 |
|
T11 |
4 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
311644 |
1 |
|
T1 |
4 |
|
T9 |
1 |
|
T10 |
9 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
31 |
1 |
|
T55 |
4 |
|
T75 |
3 |
|
T88 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
59 |
1 |
|
T55 |
1 |
|
T75 |
5 |
|
T88 |
3 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
7 |
1 |
|
T79 |
1 |
|
T132 |
1 |
|
T133 |
2 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
6 |
1 |
|
T55 |
1 |
|
T134 |
1 |
|
T130 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
38 |
1 |
|
T55 |
2 |
|
T75 |
4 |
|
T88 |
3 |
auto[TlIntgErrData] |
partial |
auto[1] |
51 |
1 |
|
T55 |
5 |
|
T75 |
3 |
|
T88 |
5 |
auto[TlIntgErrData] |
full_word |
auto[0] |
9 |
1 |
|
T75 |
1 |
|
T79 |
1 |
|
T127 |
2 |
auto[TlIntgErrData] |
full_word |
auto[1] |
4 |
1 |
|
T75 |
1 |
|
T129 |
1 |
|
T130 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
43 |
1 |
|
T55 |
3 |
|
T75 |
1 |
|
T88 |
5 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
46 |
1 |
|
T55 |
3 |
|
T75 |
2 |
|
T88 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
3 |
1 |
|
T127 |
1 |
|
T129 |
1 |
|
T130 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
3 |
1 |
|
T55 |
1 |
|
T88 |
1 |
|
T126 |
1 |