Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.90	96.97	55.32	84.72		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	129878313	18598	0	0
late_debug_enable_rd_A	129878313	2763	0	0
late_debug_enable_regwen_rd_A	129878313	3653	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129878313	18598	0	0
T51	513790	309	0	0
T55	100957	3	0	0
T56	104886	19	0	0
T57	4461	551	0	0
T58	12686	254	0	0
T75	263823	5	0	0
T76	15169	539	0	0
T77	49450	1	0	0
T78	219908	288	0	0
T88	134999	6	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129878313	2763	0	0
T52	834740	172	0	0
T56	104886	9	0	0
T61	247496	153	0	0
T75	263823	80	0	0
T76	15169	203	0	0
T77	49450	16	0	0
T80	16988	23	0	0
T100	8150	3	0	0
T123	16439	70	0	0
T124	146659	49	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129878313	3653	0	0
T52	834740	200	0	0
T56	104886	6	0	0
T61	247496	142	0	0
T75	263823	79	0	0
T76	15169	178	0	0
T77	49450	29	0	0
T80	16988	15	0	0
T100	8150	1	0	0
T101	375886	1024	0	0
T123	16439	91	0	0