SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rv_dm_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 129878313 | 18598 | 0 | 0 |
late_debug_enable_rd_A | 129878313 | 2763 | 0 | 0 |
late_debug_enable_regwen_rd_A | 129878313 | 3653 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 129878313 | 18598 | 0 | 0 |
T51 | 513790 | 309 | 0 | 0 |
T55 | 100957 | 3 | 0 | 0 |
T56 | 104886 | 19 | 0 | 0 |
T57 | 4461 | 551 | 0 | 0 |
T58 | 12686 | 254 | 0 | 0 |
T75 | 263823 | 5 | 0 | 0 |
T76 | 15169 | 539 | 0 | 0 |
T77 | 49450 | 1 | 0 | 0 |
T78 | 219908 | 288 | 0 | 0 |
T88 | 134999 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 129878313 | 2763 | 0 | 0 |
T52 | 834740 | 172 | 0 | 0 |
T56 | 104886 | 9 | 0 | 0 |
T61 | 247496 | 153 | 0 | 0 |
T75 | 263823 | 80 | 0 | 0 |
T76 | 15169 | 203 | 0 | 0 |
T77 | 49450 | 16 | 0 | 0 |
T80 | 16988 | 23 | 0 | 0 |
T100 | 8150 | 3 | 0 | 0 |
T123 | 16439 | 70 | 0 | 0 |
T124 | 146659 | 49 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 129878313 | 3653 | 0 | 0 |
T52 | 834740 | 200 | 0 | 0 |
T56 | 104886 | 6 | 0 | 0 |
T61 | 247496 | 142 | 0 | 0 |
T75 | 263823 | 79 | 0 | 0 |
T76 | 15169 | 178 | 0 | 0 |
T77 | 49450 | 29 | 0 | 0 |
T80 | 16988 | 15 | 0 | 0 |
T100 | 8150 | 1 | 0 | 0 |
T101 | 375886 | 1024 | 0 | 0 |
T123 | 16439 | 91 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |