Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9304443 |
9303241 |
0 |
0 |
selKnown1 |
66682115 |
66680913 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9304443 |
9303241 |
0 |
0 |
T1 |
44157 |
44153 |
0 |
0 |
T2 |
218 |
214 |
0 |
0 |
T3 |
21480 |
21476 |
0 |
0 |
T4 |
266 |
262 |
0 |
0 |
T5 |
2766 |
2762 |
0 |
0 |
T8 |
0 |
6 |
0 |
0 |
T11 |
0 |
24 |
0 |
0 |
T12 |
12350 |
12346 |
0 |
0 |
T15 |
22266 |
22262 |
0 |
0 |
T18 |
0 |
8 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T20 |
0 |
6 |
0 |
0 |
T30 |
0 |
10 |
0 |
0 |
T31 |
266 |
262 |
0 |
0 |
T32 |
300 |
296 |
0 |
0 |
T33 |
218 |
214 |
0 |
0 |
T48 |
0 |
20 |
0 |
0 |
T65 |
0 |
6 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
66682115 |
66680913 |
0 |
0 |
T1 |
545624 |
545620 |
0 |
0 |
T2 |
6598 |
6594 |
0 |
0 |
T3 |
117942 |
117938 |
0 |
0 |
T4 |
3810 |
3806 |
0 |
0 |
T5 |
13553 |
13549 |
0 |
0 |
T8 |
0 |
6 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T12 |
351883 |
351879 |
0 |
0 |
T15 |
266691 |
266687 |
0 |
0 |
T18 |
0 |
8 |
0 |
0 |
T19 |
0 |
2 |
0 |
0 |
T20 |
0 |
6 |
0 |
0 |
T30 |
0 |
8 |
0 |
0 |
T31 |
3263 |
3259 |
0 |
0 |
T32 |
2657 |
2653 |
0 |
0 |
T33 |
1786 |
1782 |
0 |
0 |
T48 |
0 |
20 |
0 |
0 |
T65 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2865756 |
2865563 |
0 |
0 |
selKnown1 |
60243670 |
60243477 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2865756 |
2865563 |
0 |
0 |
T1 |
22062 |
22061 |
0 |
0 |
T2 |
108 |
107 |
0 |
0 |
T3 |
10739 |
10738 |
0 |
0 |
T4 |
132 |
131 |
0 |
0 |
T5 |
1372 |
1371 |
0 |
0 |
T12 |
6174 |
6173 |
0 |
0 |
T15 |
11132 |
11131 |
0 |
0 |
T31 |
132 |
131 |
0 |
0 |
T32 |
149 |
148 |
0 |
0 |
T33 |
108 |
107 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
60243670 |
60243477 |
0 |
0 |
T1 |
523556 |
523555 |
0 |
0 |
T2 |
6488 |
6487 |
0 |
0 |
T3 |
107201 |
107200 |
0 |
0 |
T4 |
3676 |
3675 |
0 |
0 |
T5 |
12159 |
12158 |
0 |
0 |
T12 |
345707 |
345706 |
0 |
0 |
T15 |
255557 |
255556 |
0 |
0 |
T31 |
3129 |
3128 |
0 |
0 |
T32 |
2506 |
2505 |
0 |
0 |
T33 |
1676 |
1675 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526 |
333 |
0 |
0 |
T1 |
16 |
15 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T11 |
0 |
12 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T20 |
0 |
3 |
0 |
0 |
T30 |
0 |
4 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T48 |
0 |
10 |
0 |
0 |
T65 |
0 |
3 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449 |
256 |
0 |
0 |
T1 |
3 |
2 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T20 |
0 |
3 |
0 |
0 |
T30 |
0 |
4 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T48 |
0 |
10 |
0 |
0 |
T65 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6436533 |
6436125 |
0 |
0 |
selKnown1 |
6436533 |
6436125 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6436533 |
6436125 |
0 |
0 |
T1 |
22062 |
22061 |
0 |
0 |
T2 |
108 |
107 |
0 |
0 |
T3 |
10739 |
10738 |
0 |
0 |
T4 |
132 |
131 |
0 |
0 |
T5 |
1372 |
1371 |
0 |
0 |
T12 |
6174 |
6173 |
0 |
0 |
T15 |
11132 |
11131 |
0 |
0 |
T31 |
132 |
131 |
0 |
0 |
T32 |
149 |
148 |
0 |
0 |
T33 |
108 |
107 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6436533 |
6436125 |
0 |
0 |
T1 |
22062 |
22061 |
0 |
0 |
T2 |
108 |
107 |
0 |
0 |
T3 |
10739 |
10738 |
0 |
0 |
T4 |
132 |
131 |
0 |
0 |
T5 |
1372 |
1371 |
0 |
0 |
T12 |
6174 |
6173 |
0 |
0 |
T15 |
11132 |
11131 |
0 |
0 |
T31 |
132 |
131 |
0 |
0 |
T32 |
149 |
148 |
0 |
0 |
T33 |
108 |
107 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1628 |
1220 |
0 |
0 |
selKnown1 |
1463 |
1055 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1628 |
1220 |
0 |
0 |
T1 |
17 |
16 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T11 |
0 |
12 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T20 |
0 |
3 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T48 |
0 |
10 |
0 |
0 |
T65 |
0 |
3 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1463 |
1055 |
0 |
0 |
T1 |
3 |
2 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
11 |
10 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T19 |
0 |
1 |
0 |
0 |
T20 |
0 |
3 |
0 |
0 |
T30 |
0 |
4 |
0 |
0 |
T31 |
1 |
0 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T48 |
0 |
10 |
0 |
0 |
T65 |
0 |
3 |
0 |
0 |