SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
58.07 | 78.43 | 66.67 | 28.57 | 66.67 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
75.72 | 96.08 | 77.78 | 71.43 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1158 | 1158 | 0 | 0 |
OutputsKnown_A | 361462020 | 361283856 | 0 | 0 |
gen_flops.OutputDelay_A | 180731010 | 180637887 | 0 | 1737 |
gen_no_flops.OutputDelay_A | 180731010 | 180641928 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1158 | 1158 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T12 | 6 | 6 | 0 | 0 |
T15 | 6 | 6 | 0 | 0 |
T31 | 6 | 6 | 0 | 0 |
T32 | 6 | 6 | 0 | 0 |
T33 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 361462020 | 361283856 | 0 | 0 |
T1 | 3141336 | 3140256 | 0 | 0 |
T2 | 38928 | 38466 | 0 | 0 |
T3 | 643206 | 642900 | 0 | 0 |
T4 | 22056 | 21678 | 0 | 0 |
T5 | 72954 | 68424 | 0 | 0 |
T12 | 2074242 | 2073834 | 0 | 0 |
T15 | 1533342 | 1532844 | 0 | 0 |
T31 | 18774 | 18336 | 0 | 0 |
T32 | 15036 | 14598 | 0 | 0 |
T33 | 10056 | 9738 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 180731010 | 180637887 | 0 | 1737 |
T1 | 1570668 | 1570101 | 0 | 9 |
T2 | 19464 | 19224 | 0 | 9 |
T3 | 321603 | 321441 | 0 | 9 |
T4 | 11028 | 10830 | 0 | 9 |
T5 | 36477 | 34113 | 0 | 9 |
T12 | 1037121 | 1036908 | 0 | 9 |
T15 | 766671 | 766413 | 0 | 9 |
T31 | 9387 | 9159 | 0 | 9 |
T32 | 7518 | 7290 | 0 | 9 |
T33 | 5028 | 4860 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 180731010 | 180641928 | 0 | 0 |
T1 | 1570668 | 1570128 | 0 | 0 |
T2 | 19464 | 19233 | 0 | 0 |
T3 | 321603 | 321450 | 0 | 0 |
T4 | 11028 | 10839 | 0 | 0 |
T5 | 36477 | 34212 | 0 | 0 |
T12 | 1037121 | 1036917 | 0 | 0 |
T15 | 766671 | 766422 | 0 | 0 |
T31 | 9387 | 9168 | 0 | 0 |
T32 | 7518 | 7299 | 0 | 0 |
T33 | 5028 | 4869 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 60243670 | 60213976 | 0 | 0 |
gen_flops.OutputDelay_A | 60243670 | 60212629 | 0 | 579 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60213976 | 0 | 0 |
T1 | 523556 | 523376 | 0 | 0 |
T2 | 6488 | 6411 | 0 | 0 |
T3 | 107201 | 107150 | 0 | 0 |
T4 | 3676 | 3613 | 0 | 0 |
T5 | 12159 | 11404 | 0 | 0 |
T12 | 345707 | 345639 | 0 | 0 |
T15 | 255557 | 255474 | 0 | 0 |
T31 | 3129 | 3056 | 0 | 0 |
T32 | 2506 | 2433 | 0 | 0 |
T33 | 1676 | 1623 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60212629 | 0 | 579 |
T1 | 523556 | 523367 | 0 | 3 |
T2 | 6488 | 6408 | 0 | 3 |
T3 | 107201 | 107147 | 0 | 3 |
T4 | 3676 | 3610 | 0 | 3 |
T5 | 12159 | 11371 | 0 | 3 |
T12 | 345707 | 345636 | 0 | 3 |
T15 | 255557 | 255471 | 0 | 3 |
T31 | 3129 | 3053 | 0 | 3 |
T32 | 2506 | 2430 | 0 | 3 |
T33 | 1676 | 1620 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 60243670 | 60213976 | 0 | 0 |
gen_flops.OutputDelay_A | 60243670 | 60212629 | 0 | 579 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60213976 | 0 | 0 |
T1 | 523556 | 523376 | 0 | 0 |
T2 | 6488 | 6411 | 0 | 0 |
T3 | 107201 | 107150 | 0 | 0 |
T4 | 3676 | 3613 | 0 | 0 |
T5 | 12159 | 11404 | 0 | 0 |
T12 | 345707 | 345639 | 0 | 0 |
T15 | 255557 | 255474 | 0 | 0 |
T31 | 3129 | 3056 | 0 | 0 |
T32 | 2506 | 2433 | 0 | 0 |
T33 | 1676 | 1623 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60212629 | 0 | 579 |
T1 | 523556 | 523367 | 0 | 3 |
T2 | 6488 | 6408 | 0 | 3 |
T3 | 107201 | 107147 | 0 | 3 |
T4 | 3676 | 3610 | 0 | 3 |
T5 | 12159 | 11371 | 0 | 3 |
T12 | 345707 | 345636 | 0 | 3 |
T15 | 255557 | 255471 | 0 | 3 |
T31 | 3129 | 3053 | 0 | 3 |
T32 | 2506 | 2430 | 0 | 3 |
T33 | 1676 | 1620 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 60243670 | 60213976 | 0 | 0 |
gen_no_flops.OutputDelay_A | 60243670 | 60213976 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60213976 | 0 | 0 |
T1 | 523556 | 523376 | 0 | 0 |
T2 | 6488 | 6411 | 0 | 0 |
T3 | 107201 | 107150 | 0 | 0 |
T4 | 3676 | 3613 | 0 | 0 |
T5 | 12159 | 11404 | 0 | 0 |
T12 | 345707 | 345639 | 0 | 0 |
T15 | 255557 | 255474 | 0 | 0 |
T31 | 3129 | 3056 | 0 | 0 |
T32 | 2506 | 2433 | 0 | 0 |
T33 | 1676 | 1623 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60213976 | 0 | 0 |
T1 | 523556 | 523376 | 0 | 0 |
T2 | 6488 | 6411 | 0 | 0 |
T3 | 107201 | 107150 | 0 | 0 |
T4 | 3676 | 3613 | 0 | 0 |
T5 | 12159 | 11404 | 0 | 0 |
T12 | 345707 | 345639 | 0 | 0 |
T15 | 255557 | 255474 | 0 | 0 |
T31 | 3129 | 3056 | 0 | 0 |
T32 | 2506 | 2433 | 0 | 0 |
T33 | 1676 | 1623 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 60243670 | 60213976 | 0 | 0 |
gen_flops.OutputDelay_A | 60243670 | 60212629 | 0 | 579 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60213976 | 0 | 0 |
T1 | 523556 | 523376 | 0 | 0 |
T2 | 6488 | 6411 | 0 | 0 |
T3 | 107201 | 107150 | 0 | 0 |
T4 | 3676 | 3613 | 0 | 0 |
T5 | 12159 | 11404 | 0 | 0 |
T12 | 345707 | 345639 | 0 | 0 |
T15 | 255557 | 255474 | 0 | 0 |
T31 | 3129 | 3056 | 0 | 0 |
T32 | 2506 | 2433 | 0 | 0 |
T33 | 1676 | 1623 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60212629 | 0 | 579 |
T1 | 523556 | 523367 | 0 | 3 |
T2 | 6488 | 6408 | 0 | 3 |
T3 | 107201 | 107147 | 0 | 3 |
T4 | 3676 | 3610 | 0 | 3 |
T5 | 12159 | 11371 | 0 | 3 |
T12 | 345707 | 345636 | 0 | 3 |
T15 | 255557 | 255471 | 0 | 3 |
T31 | 3129 | 3053 | 0 | 3 |
T32 | 2506 | 2430 | 0 | 3 |
T33 | 1676 | 1620 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 60243670 | 60213976 | 0 | 0 |
gen_no_flops.OutputDelay_A | 60243670 | 60213976 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60213976 | 0 | 0 |
T1 | 523556 | 523376 | 0 | 0 |
T2 | 6488 | 6411 | 0 | 0 |
T3 | 107201 | 107150 | 0 | 0 |
T4 | 3676 | 3613 | 0 | 0 |
T5 | 12159 | 11404 | 0 | 0 |
T12 | 345707 | 345639 | 0 | 0 |
T15 | 255557 | 255474 | 0 | 0 |
T31 | 3129 | 3056 | 0 | 0 |
T32 | 2506 | 2433 | 0 | 0 |
T33 | 1676 | 1623 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60213976 | 0 | 0 |
T1 | 523556 | 523376 | 0 | 0 |
T2 | 6488 | 6411 | 0 | 0 |
T3 | 107201 | 107150 | 0 | 0 |
T4 | 3676 | 3613 | 0 | 0 |
T5 | 12159 | 11404 | 0 | 0 |
T12 | 345707 | 345639 | 0 | 0 |
T15 | 255557 | 255474 | 0 | 0 |
T31 | 3129 | 3056 | 0 | 0 |
T32 | 2506 | 2433 | 0 | 0 |
T33 | 1676 | 1623 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 60243670 | 60213976 | 0 | 0 |
gen_no_flops.OutputDelay_A | 60243670 | 60213976 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60213976 | 0 | 0 |
T1 | 523556 | 523376 | 0 | 0 |
T2 | 6488 | 6411 | 0 | 0 |
T3 | 107201 | 107150 | 0 | 0 |
T4 | 3676 | 3613 | 0 | 0 |
T5 | 12159 | 11404 | 0 | 0 |
T12 | 345707 | 345639 | 0 | 0 |
T15 | 255557 | 255474 | 0 | 0 |
T31 | 3129 | 3056 | 0 | 0 |
T32 | 2506 | 2433 | 0 | 0 |
T33 | 1676 | 1623 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 60243670 | 60213976 | 0 | 0 |
T1 | 523556 | 523376 | 0 | 0 |
T2 | 6488 | 6411 | 0 | 0 |
T3 | 107201 | 107150 | 0 | 0 |
T4 | 3676 | 3613 | 0 | 0 |
T5 | 12159 | 11404 | 0 | 0 |
T12 | 345707 | 345639 | 0 | 0 |
T15 | 255557 | 255474 | 0 | 0 |
T31 | 3129 | 3056 | 0 | 0 |
T32 | 2506 | 2433 | 0 | 0 |
T33 | 1676 | 1623 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |