Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 204221 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 555829 1 T16 2 T9 19 T10 4



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 483646 1 T9 16 T5 10 T6 18
values[0x0] 134992 1 T8 2 T16 2 T9 7
values[0x1] 141412 1 T8 4 T9 11 T10 6



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 154146 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 605904 1 T8 2 T16 2 T9 21



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2821 1 T27 1 T56 3 T57 1
valid_sources[0x01] 3119 1 T6 2 T25 1 T56 1
valid_sources[0x02] 2795 1 T6 2 T143 1 T54 1
valid_sources[0x03] 3017 1 T19 1 T143 1 T29 2
valid_sources[0x04] 2888 1 T18 1 T56 1 T57 2
valid_sources[0x05] 2842 1 T9 1 T6 1 T27 1
valid_sources[0x06] 3039 1 T143 1 T25 2 T56 3
valid_sources[0x07] 2650 1 T6 2 T19 1 T18 1
valid_sources[0x08] 3519 1 T9 1 T143 1 T12 1
valid_sources[0x09] 2950 1 T9 1 T6 1 T32 1
valid_sources[0x0a] 2692 1 T20 1 T143 4 T54 1
valid_sources[0x0b] 3309 1 T6 1 T12 1 T144 1
valid_sources[0x0c] 2787 1 T27 1 T18 1 T143 1
valid_sources[0x0d] 2671 1 T6 1 T145 1 T56 2
valid_sources[0x0e] 2814 1 T143 1 T56 2 T57 5
valid_sources[0x0f] 3034 1 T19 4 T25 1 T57 3
valid_sources[0x10] 2787 1 T9 2 T146 1 T56 1
valid_sources[0x11] 2800 1 T6 1 T29 1 T54 2
valid_sources[0x12] 3106 1 T26 4 T143 1 T56 4
valid_sources[0x13] 2754 1 T147 5 T145 1 T56 3
valid_sources[0x14] 2730 1 T13 3 T56 2 T57 1
valid_sources[0x15] 2966 1 T9 2 T5 1 T6 1
valid_sources[0x16] 2911 1 T25 1 T57 3 T58 5
valid_sources[0x17] 2880 1 T6 2 T56 3 T57 1
valid_sources[0x18] 3571 1 T56 2 T57 2 T58 15
valid_sources[0x19] 2687 1 T29 10 T25 1 T56 1
valid_sources[0x1a] 2802 1 T9 1 T143 1 T12 1
valid_sources[0x1b] 3042 1 T5 1 T30 1 T148 1
valid_sources[0x1c] 2697 1 T27 1 T12 1 T145 1
valid_sources[0x1d] 2827 1 T12 1 T148 1 T25 1
valid_sources[0x1e] 2909 1 T12 1 T25 5 T13 5
valid_sources[0x1f] 3054 1 T9 1 T6 1 T87 1
valid_sources[0x20] 2942 1 T5 1 T148 1 T25 1
valid_sources[0x21] 2917 1 T9 1 T19 1 T25 1
valid_sources[0x22] 3492 1 T143 2 T29 1 T148 1
valid_sources[0x23] 2585 1 T143 1 T56 3 T88 222
valid_sources[0x24] 2782 1 T148 1 T56 4 T54 1
valid_sources[0x25] 2722 1 T6 1 T27 1 T149 1
valid_sources[0x26] 3166 1 T9 1 T18 1 T25 2
valid_sources[0x27] 3355 1 T5 4 T146 1 T56 3
valid_sources[0x28] 2851 1 T6 1 T20 1 T56 3
valid_sources[0x29] 2624 1 T13 1 T145 1 T150 1
valid_sources[0x2a] 3016 1 T8 6 T5 1 T19 3
valid_sources[0x2b] 2908 1 T10 3 T12 1 T56 4
valid_sources[0x2c] 3068 1 T19 1 T143 1 T12 1
valid_sources[0x2d] 3322 1 T19 1 T30 1 T145 1
valid_sources[0x2e] 2867 1 T5 1 T32 1 T143 1
valid_sources[0x2f] 2639 1 T6 2 T20 1 T57 8
valid_sources[0x30] 3583 1 T16 1 T5 3 T18 1
valid_sources[0x31] 2843 1 T143 1 T148 1 T57 3
valid_sources[0x32] 3159 1 T148 2 T145 1 T56 1
valid_sources[0x33] 2658 1 T10 1 T6 1 T32 1
valid_sources[0x34] 2711 1 T151 2 T29 1 T145 1
valid_sources[0x35] 2987 1 T147 1 T25 2 T56 6
valid_sources[0x36] 3372 1 T12 1 T150 1 T57 10
valid_sources[0x37] 3840 1 T5 1 T19 1 T13 1
valid_sources[0x38] 2894 1 T56 2 T58 9 T88 226
valid_sources[0x39] 3130 1 T86 14 T12 1 T148 1
valid_sources[0x3a] 3077 1 T18 2 T12 1 T54 3
valid_sources[0x3b] 2570 1 T9 2 T6 4 T25 2
valid_sources[0x3c] 2773 1 T19 1 T32 1 T29 2
valid_sources[0x3d] 3072 1 T5 1 T6 1 T25 1
valid_sources[0x3e] 2612 1 T143 1 T25 1 T145 1
valid_sources[0x3f] 2826 1 T25 1 T145 1 T56 3
valid_sources[0x40] 2776 1 T9 1 T143 1 T148 2
valid_sources[0x41] 3157 1 T148 1 T145 2 T146 2
valid_sources[0x42] 3015 1 T148 1 T57 2 T54 5
valid_sources[0x43] 3281 1 T152 37 T145 1 T57 2
valid_sources[0x44] 2989 1 T29 2 T145 1 T56 1
valid_sources[0x45] 2811 1 T27 2 T143 1 T12 1
valid_sources[0x46] 2701 1 T148 1 T150 1 T56 2
valid_sources[0x47] 3007 1 T5 2 T143 2 T148 1
valid_sources[0x48] 2665 1 T12 1 T56 2 T58 9
valid_sources[0x49] 2926 1 T5 2 T148 1 T56 4
valid_sources[0x4a] 3483 1 T9 1 T143 2 T56 3
valid_sources[0x4b] 2902 1 T15 12 T18 1 T143 1
valid_sources[0x4c] 2675 1 T25 1 T13 1 T150 1
valid_sources[0x4d] 2759 1 T12 1 T56 2 T54 3
valid_sources[0x4e] 2744 1 T143 3 T56 2 T57 5
valid_sources[0x4f] 2837 1 T13 1 T56 2 T54 1
valid_sources[0x50] 3250 1 T6 1 T26 1 T56 4
valid_sources[0x51] 2895 1 T12 1 T145 1 T56 2
valid_sources[0x52] 2890 1 T25 1 T54 2 T58 14
valid_sources[0x53] 2841 1 T143 1 T56 2 T57 2
valid_sources[0x54] 2850 1 T25 1 T56 2 T58 11
valid_sources[0x55] 2795 1 T148 1 T56 3 T57 2
valid_sources[0x56] 2840 1 T87 1 T145 1 T56 2
valid_sources[0x57] 3012 1 T6 1 T56 2 T57 3
valid_sources[0x58] 3856 1 T10 1 T143 3 T29 4
valid_sources[0x59] 2831 1 T20 1 T29 2 T146 2
valid_sources[0x5a] 3470 1 T143 1 T12 2 T56 2
valid_sources[0x5b] 2672 1 T29 2 T12 1 T147 2
valid_sources[0x5c] 3114 1 T57 3 T54 1 T58 22
valid_sources[0x5d] 3077 1 T5 1 T143 1 T56 5
valid_sources[0x5e] 2646 1 T6 1 T12 1 T148 1
valid_sources[0x5f] 3088 1 T6 1 T31 3 T56 2
valid_sources[0x60] 2808 1 T5 1 T45 41 T143 1
valid_sources[0x61] 3099 1 T6 1 T25 2 T58 8
valid_sources[0x62] 3482 1 T143 1 T12 1 T56 2
valid_sources[0x63] 2845 1 T145 1 T146 2 T56 2
valid_sources[0x64] 2801 1 T12 2 T25 1 T145 1
valid_sources[0x65] 2775 1 T148 1 T147 2 T56 7
valid_sources[0x66] 2742 1 T143 2 T25 1 T13 1
valid_sources[0x67] 2741 1 T9 1 T6 1 T148 1
valid_sources[0x68] 3596 1 T9 1 T56 1 T57 4
valid_sources[0x69] 3095 1 T87 1 T143 1 T144 2
valid_sources[0x6a] 3518 1 T9 1 T6 2 T18 1
valid_sources[0x6b] 2821 1 T148 1 T25 1 T145 1
valid_sources[0x6c] 2885 1 T5 5 T6 2 T148 1
valid_sources[0x6d] 3235 1 T25 1 T145 1 T56 2
valid_sources[0x6e] 3565 1 T5 1 T32 1 T143 2
valid_sources[0x6f] 2845 1 T58 18 T88 239 T51 39
valid_sources[0x70] 2733 1 T19 1 T145 1 T56 3
valid_sources[0x71] 2693 1 T6 1 T12 1 T146 3
valid_sources[0x72] 3028 1 T150 1 T57 7 T54 2
valid_sources[0x73] 2918 1 T5 1 T29 3 T148 1
valid_sources[0x74] 3319 1 T5 2 T6 3 T153 22
valid_sources[0x75] 2951 1 T149 1 T154 88 T56 5
valid_sources[0x76] 3535 1 T145 1 T56 6 T54 2
valid_sources[0x77] 2769 1 T7 2 T143 1 T56 4
valid_sources[0x78] 2979 1 T56 5 T57 1 T58 8
valid_sources[0x79] 2613 1 T6 1 T143 1 T144 2
valid_sources[0x7a] 2781 1 T56 1 T58 22 T88 173
valid_sources[0x7b] 2919 1 T143 1 T56 1 T54 4
valid_sources[0x7c] 2923 1 T143 1 T56 3 T57 2
valid_sources[0x7d] 3095 1 T19 2 T28 18 T56 2
valid_sources[0x7e] 3630 1 T9 1 T6 1 T13 1
valid_sources[0x7f] 2452 1 T9 1 T148 2 T54 2
valid_sources[0x80] 2848 1 T19 1 T25 1 T150 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 290363 1 T9 8 T5 4 T6 7
values[0x0] all_enables biggest_size 133001 1 T16 2 T9 5 T10 3
values[0x1] all_enables biggest_size 132465 1 T9 6 T10 1 T15 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4593 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 22725 1 T35 2 T38 3 T75 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 9836 1 T56 3 T57 3 T54 124
values[0x0] 8667 1 T35 5 T37 2 T38 2
values[0x1] 8815 1 T35 7 T37 7 T38 5



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3426 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 23892 1 T35 3 T37 1 T38 3



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 114 1 T59 3 T155 1 T54 1
valid_sources[0x01] 128 1 T54 3 T52 1 T81 2
valid_sources[0x02] 99 1 T56 2 T54 2 T52 1
valid_sources[0x03] 91 1 T156 1 T54 1 T52 1
valid_sources[0x04] 90 1 T55 3 T52 1 T74 1
valid_sources[0x05] 97 1 T54 1 T90 1 T82 1
valid_sources[0x06] 112 1 T54 3 T51 2 T74 1
valid_sources[0x07] 96 1 T54 1 T51 1 T55 1
valid_sources[0x08] 116 1 T54 2 T55 1 T52 1
valid_sources[0x09] 98 1 T157 1 T74 4 T81 2
valid_sources[0x0a] 94 1 T158 3 T54 1 T52 1
valid_sources[0x0b] 67 1 T35 2 T84 2 T85 2
valid_sources[0x0c] 142 1 T80 1 T74 6 T81 1
valid_sources[0x0d] 110 1 T54 3 T51 2 T52 1
valid_sources[0x0e] 72 1 T54 3 T81 1 T82 1
valid_sources[0x0f] 97 1 T159 2 T54 1 T51 2
valid_sources[0x10] 139 1 T88 55 T51 1 T55 1
valid_sources[0x11] 142 1 T79 1 T54 1 T51 1
valid_sources[0x12] 123 1 T160 3 T53 22 T74 2
valid_sources[0x13] 156 1 T54 3 T51 1 T55 1
valid_sources[0x14] 98 1 T161 1 T54 3 T52 1
valid_sources[0x15] 109 1 T54 2 T74 3 T82 1
valid_sources[0x16] 102 1 T54 2 T52 1 T74 1
valid_sources[0x17] 130 1 T162 1 T163 1 T54 1
valid_sources[0x18] 78 1 T59 3 T164 1 T54 3
valid_sources[0x19] 98 1 T165 1 T54 3 T52 2
valid_sources[0x1a] 132 1 T54 1 T51 4 T52 1
valid_sources[0x1b] 97 1 T54 3 T80 1 T74 1
valid_sources[0x1c] 243 1 T88 140 T52 2 T53 2
valid_sources[0x1d] 124 1 T53 9 T80 1 T74 1
valid_sources[0x1e] 91 1 T126 1 T166 1 T54 4
valid_sources[0x1f] 68 1 T163 1 T54 1 T55 1
valid_sources[0x20] 92 1 T56 1 T54 2 T53 3
valid_sources[0x21] 88 1 T157 2 T54 3 T52 1
valid_sources[0x22] 81 1 T167 2 T54 2 T55 2
valid_sources[0x23] 116 1 T162 1 T56 1 T54 3
valid_sources[0x24] 102 1 T35 1 T77 2 T54 4
valid_sources[0x25] 96 1 T54 6 T51 4 T52 1
valid_sources[0x26] 73 1 T37 1 T161 2 T54 3
valid_sources[0x27] 110 1 T38 1 T51 4 T52 2
valid_sources[0x28] 98 1 T54 3 T51 2 T74 3
valid_sources[0x29] 101 1 T129 1 T51 1 T52 1
valid_sources[0x2a] 141 1 T54 1 T51 1 T55 3
valid_sources[0x2b] 102 1 T48 2 T77 1 T168 1
valid_sources[0x2c] 102 1 T54 2 T51 5 T80 1
valid_sources[0x2d] 87 1 T155 1 T168 4 T54 1
valid_sources[0x2e] 101 1 T169 11 T55 1 T81 1
valid_sources[0x2f] 98 1 T77 1 T52 1 T74 1
valid_sources[0x30] 100 1 T170 1 T54 2 T52 1
valid_sources[0x31] 94 1 T54 5 T51 3 T52 1
valid_sources[0x32] 91 1 T37 1 T157 2 T54 2
valid_sources[0x33] 132 1 T126 2 T54 2 T80 1
valid_sources[0x34] 100 1 T162 2 T163 1 T55 1
valid_sources[0x35] 102 1 T55 2 T52 3 T74 5
valid_sources[0x36] 128 1 T162 2 T171 5 T52 1
valid_sources[0x37] 107 1 T127 1 T129 1 T172 1
valid_sources[0x38] 104 1 T54 1 T51 5 T55 1
valid_sources[0x39] 57 1 T57 1 T55 2 T74 5
valid_sources[0x3a] 108 1 T173 5 T54 3 T74 3
valid_sources[0x3b] 89 1 T163 1 T51 1 T52 2
valid_sources[0x3c] 64 1 T54 1 T51 2 T55 4
valid_sources[0x3d] 79 1 T52 1 T81 1 T84 2
valid_sources[0x3e] 106 1 T162 1 T167 2 T54 4
valid_sources[0x3f] 76 1 T51 1 T55 1 T52 1
valid_sources[0x40] 73 1 T54 1 T52 1 T82 1
valid_sources[0x41] 115 1 T166 1 T54 1 T74 2
valid_sources[0x42] 108 1 T76 13 T129 1 T166 1
valid_sources[0x43] 95 1 T72 18 T74 2 T81 1
valid_sources[0x44] 98 1 T164 2 T74 3 T84 6
valid_sources[0x45] 127 1 T161 1 T54 1 T74 3
valid_sources[0x46] 115 1 T37 1 T54 1 T55 1
valid_sources[0x47] 103 1 T77 1 T55 3 T52 1
valid_sources[0x48] 110 1 T174 2 T166 1 T52 1
valid_sources[0x49] 85 1 T157 1 T56 1 T54 1
valid_sources[0x4a] 75 1 T54 4 T74 1 T90 2
valid_sources[0x4b] 71 1 T166 2 T54 3 T51 1
valid_sources[0x4c] 151 1 T54 2 T52 1 T84 1
valid_sources[0x4d] 108 1 T54 2 T55 2 T53 3
valid_sources[0x4e] 98 1 T74 8 T84 5 T105 3
valid_sources[0x4f] 106 1 T35 2 T175 1 T54 1
valid_sources[0x50] 95 1 T52 2 T53 3 T80 1
valid_sources[0x51] 79 1 T54 3 T55 1 T74 1
valid_sources[0x52] 98 1 T54 4 T51 1 T81 1
valid_sources[0x53] 110 1 T157 1 T51 2 T52 1
valid_sources[0x54] 98 1 T170 4 T157 1 T80 1
valid_sources[0x55] 169 1 T59 2 T163 1 T74 3
valid_sources[0x56] 77 1 T162 2 T51 2 T74 1
valid_sources[0x57] 102 1 T54 3 T55 1 T74 1
valid_sources[0x58] 95 1 T54 3 T51 2 T55 6
valid_sources[0x59] 95 1 T173 3 T54 1 T51 1
valid_sources[0x5a] 78 1 T54 1 T80 1 T74 1
valid_sources[0x5b] 93 1 T77 1 T54 1 T52 1
valid_sources[0x5c] 87 1 T162 1 T54 1 T51 2
valid_sources[0x5d] 86 1 T77 1 T55 1 T52 2
valid_sources[0x5e] 112 1 T77 1 T78 2 T168 1
valid_sources[0x5f] 130 1 T54 2 T51 1 T80 1
valid_sources[0x60] 111 1 T54 2 T80 1 T74 2
valid_sources[0x61] 81 1 T35 1 T54 1 T55 2
valid_sources[0x62] 154 1 T54 2 T51 3 T55 1
valid_sources[0x63] 72 1 T176 1 T166 1 T54 1
valid_sources[0x64] 85 1 T78 2 T54 2 T52 3
valid_sources[0x65] 84 1 T54 1 T51 1 T96 1
valid_sources[0x66] 89 1 T162 1 T54 3 T51 1
valid_sources[0x67] 72 1 T51 1 T84 1 T85 1
valid_sources[0x68] 88 1 T35 1 T54 1 T55 1
valid_sources[0x69] 117 1 T54 2 T51 1 T55 2
valid_sources[0x6a] 88 1 T168 1 T54 3 T74 3
valid_sources[0x6b] 93 1 T54 2 T55 1 T52 1
valid_sources[0x6c] 105 1 T54 1 T53 6 T74 1
valid_sources[0x6d] 88 1 T54 2 T51 1 T80 2
valid_sources[0x6e] 106 1 T177 7 T52 2 T74 1
valid_sources[0x6f] 113 1 T54 1 T80 2 T74 3
valid_sources[0x70] 116 1 T54 2 T74 1 T82 1
valid_sources[0x71] 98 1 T55 1 T81 1 T84 3
valid_sources[0x72] 103 1 T77 1 T165 1 T81 1
valid_sources[0x73] 97 1 T51 1 T80 1 T81 1
valid_sources[0x74] 92 1 T172 1 T54 2 T55 2
valid_sources[0x75] 90 1 T54 3 T51 1 T80 1
valid_sources[0x76] 119 1 T166 1 T54 2 T52 1
valid_sources[0x77] 116 1 T54 3 T58 12 T55 2
valid_sources[0x78] 163 1 T54 1 T84 1 T96 3
valid_sources[0x79] 101 1 T54 1 T74 5 T90 2
valid_sources[0x7a] 73 1 T168 1 T54 2 T55 1
valid_sources[0x7b] 275 1 T162 2 T55 2 T52 1
valid_sources[0x7c] 119 1 T164 2 T84 3 T85 1
valid_sources[0x7d] 81 1 T54 1 T52 1 T84 1
valid_sources[0x7e] 111 1 T54 3 T55 3 T74 3
valid_sources[0x7f] 111 1 T54 2 T58 6 T51 2
valid_sources[0x80] 146 1 T55 1 T74 6 T81 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7262 1 T56 2 T57 1 T54 121
values[0x0] all_enables biggest_size 7913 1 T35 2 T38 1 T76 3
values[0x1] all_enables biggest_size 7550 1 T38 2 T75 1 T77 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%