SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 791997 | 1 | T8 | 6 | T16 | 2 | T9 | 34 | |||
auto[1] | 28073 | 1 | T24 | 80 | T25 | 80 | T54 | 738 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 819868 | 1 | T8 | 6 | T16 | 2 | T9 | 34 | |||
values[1] | 20 | 1 | T51 | 1 | T52 | 1 | T80 | 1 | |||
values[2] | 4 | 1 | T85 | 1 | T131 | 1 | T132 | 1 | |||
values[3] | 112 | 1 | T51 | 5 | T52 | 8 | T53 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 819853 | 1 | T8 | 6 | T16 | 2 | T9 | 34 | |||
values[1] | 21 | 1 | T51 | 3 | T52 | 2 | T53 | 1 | |||
values[2] | 6 | 1 | T51 | 1 | T52 | 1 | T53 | 1 | |||
values[3] | 116 | 1 | T51 | 4 | T52 | 5 | T53 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 819750 | 1 | T8 | 6 | T16 | 2 | T9 | 34 | |||
auto[TlIntgErrCmd] | 103 | 1 | T51 | 7 | T52 | 4 | T53 | 9 | |||
auto[TlIntgErrData] | 118 | 1 | T51 | 9 | T52 | 6 | T53 | 5 | |||
auto[TlIntgErrBoth] | 99 | 1 | T51 | 4 | T52 | 10 | T53 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 53348 | 0 | T35 | 12 | T37 | 9 | T38 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 53132 | 1 | T35 | 12 | T37 | 9 | T38 | 7 | |||
values[1] | 22 | 1 | T52 | 2 | T53 | 1 | T80 | 1 | |||
values[2] | 4 | 1 | T133 | 1 | T132 | 1 | T134 | 1 | |||
values[3] | 105 | 1 | T51 | 6 | T52 | 6 | T53 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 53133 | 1 | T35 | 12 | T37 | 9 | T38 | 7 | |||
values[1] | 22 | 1 | T51 | 1 | T53 | 2 | T85 | 1 | |||
values[2] | 8 | 1 | T51 | 1 | T80 | 2 | T85 | 1 | |||
values[3] | 107 | 1 | T51 | 7 | T52 | 7 | T53 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 53028 | 1 | T35 | 12 | T37 | 9 | T38 | 7 | |||
auto[TlIntgErrCmd] | 105 | 1 | T51 | 7 | T52 | 8 | T53 | 7 | |||
auto[TlIntgErrData] | 104 | 1 | T51 | 4 | T52 | 7 | T53 | 4 | |||
auto[TlIntgErrBoth] | 111 | 1 | T51 | 9 | T52 | 5 | T53 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |