Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
261858 |
1 |
|
T8 |
6 |
|
T9 |
15 |
|
T10 |
12 |
full_word |
558212 |
1 |
|
T16 |
2 |
|
T9 |
19 |
|
T10 |
4 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
819750 |
1 |
|
T8 |
6 |
|
T16 |
2 |
|
T9 |
34 |
auto[TlIntgErrCmd] |
103 |
1 |
|
T51 |
7 |
|
T52 |
4 |
|
T53 |
9 |
auto[TlIntgErrData] |
118 |
1 |
|
T51 |
9 |
|
T52 |
6 |
|
T53 |
5 |
auto[TlIntgErrBoth] |
99 |
1 |
|
T51 |
4 |
|
T52 |
10 |
|
T53 |
6 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
486616 |
1 |
|
T9 |
16 |
|
T5 |
10 |
|
T6 |
18 |
auto[1] |
333454 |
1 |
|
T8 |
6 |
|
T16 |
2 |
|
T9 |
18 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
195801 |
1 |
|
T9 |
8 |
|
T5 |
6 |
|
T6 |
11 |
auto[TlIntgErrNone] |
partial |
auto[1] |
65764 |
1 |
|
T8 |
6 |
|
T9 |
7 |
|
T10 |
12 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
290654 |
1 |
|
T9 |
8 |
|
T5 |
4 |
|
T6 |
7 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
267531 |
1 |
|
T16 |
2 |
|
T9 |
11 |
|
T10 |
4 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
49 |
1 |
|
T51 |
5 |
|
T52 |
2 |
|
T53 |
2 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
48 |
1 |
|
T51 |
1 |
|
T52 |
2 |
|
T53 |
7 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
3 |
1 |
|
T135 |
1 |
|
T136 |
2 |
|
- |
- |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
3 |
1 |
|
T51 |
1 |
|
T137 |
1 |
|
T131 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
62 |
1 |
|
T51 |
6 |
|
T53 |
2 |
|
T80 |
2 |
auto[TlIntgErrData] |
partial |
auto[1] |
43 |
1 |
|
T51 |
2 |
|
T52 |
2 |
|
T53 |
2 |
auto[TlIntgErrData] |
full_word |
auto[0] |
3 |
1 |
|
T52 |
1 |
|
T138 |
1 |
|
T139 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
10 |
1 |
|
T51 |
1 |
|
T52 |
3 |
|
T53 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
41 |
1 |
|
T52 |
3 |
|
T53 |
4 |
|
T80 |
3 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
50 |
1 |
|
T51 |
4 |
|
T52 |
6 |
|
T53 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
3 |
1 |
|
T132 |
1 |
|
T139 |
1 |
|
T140 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
5 |
1 |
|
T52 |
1 |
|
T85 |
1 |
|
T141 |
1 |