Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.90	96.97	55.32	84.72		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	112454577	19924	0	0
late_debug_enable_rd_A	112454577	5335	0	0
late_debug_enable_regwen_rd_A	112454577	4749	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112454577	19924	0	0
T51	99044	4	0	0
T52	315799	2	0	0
T53	169829	5	0	0
T54	8894	562	0	0
T55	13224	177	0	0
T74	20890	437	0	0
T80	90733	5	0	0
T81	51706	31	0	0
T82	3697	15	0	0
T83	223241	83	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112454577	5335	0	0
T53	169829	90	0	0
T56	8057	1	0	0
T58	25728	2	0	0
T74	20890	203	0	0
T80	90733	35	0	0
T81	51706	40	0	0
T83	223241	90	0	0
T84	33206	223	0	0
T88	333957	579	0	0
T90	20384	30	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112454577	4749	0	0
T53	169829	91	0	0
T56	8057	1	0	0
T58	25728	16	0	0
T74	20890	135	0	0
T80	90733	33	0	0
T81	51706	40	0	0
T83	223241	42	0	0
T84	33206	186	0	0
T88	333957	554	0	0
T90	20384	7	0	0