SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rv_dm_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 112454577 | 19924 | 0 | 0 |
late_debug_enable_rd_A | 112454577 | 5335 | 0 | 0 |
late_debug_enable_regwen_rd_A | 112454577 | 4749 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 112454577 | 19924 | 0 | 0 |
T51 | 99044 | 4 | 0 | 0 |
T52 | 315799 | 2 | 0 | 0 |
T53 | 169829 | 5 | 0 | 0 |
T54 | 8894 | 562 | 0 | 0 |
T55 | 13224 | 177 | 0 | 0 |
T74 | 20890 | 437 | 0 | 0 |
T80 | 90733 | 5 | 0 | 0 |
T81 | 51706 | 31 | 0 | 0 |
T82 | 3697 | 15 | 0 | 0 |
T83 | 223241 | 83 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 112454577 | 5335 | 0 | 0 |
T53 | 169829 | 90 | 0 | 0 |
T56 | 8057 | 1 | 0 | 0 |
T58 | 25728 | 2 | 0 | 0 |
T74 | 20890 | 203 | 0 | 0 |
T80 | 90733 | 35 | 0 | 0 |
T81 | 51706 | 40 | 0 | 0 |
T83 | 223241 | 90 | 0 | 0 |
T84 | 33206 | 223 | 0 | 0 |
T88 | 333957 | 579 | 0 | 0 |
T90 | 20384 | 30 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 112454577 | 4749 | 0 | 0 |
T53 | 169829 | 91 | 0 | 0 |
T56 | 8057 | 1 | 0 | 0 |
T58 | 25728 | 16 | 0 | 0 |
T74 | 20890 | 135 | 0 | 0 |
T80 | 90733 | 33 | 0 | 0 |
T81 | 51706 | 40 | 0 | 0 |
T83 | 223241 | 42 | 0 | 0 |
T84 | 33206 | 186 | 0 | 0 |
T88 | 333957 | 554 | 0 | 0 |
T90 | 20384 | 7 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |