Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9270058 9268834 0 0
selKnown1 62845580 62844356 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9270058 9268834 0 0
T1 31534 31532 0 0
T2 45982 45980 0 0
T3 17982 17978 0 0
T4 34094 34090 0 0
T5 0 18 0 0
T8 3396 3392 0 0
T9 0 8 0 0
T11 1108 1104 0 0
T16 836 832 0 0
T17 43840 43836 0 0
T35 226 222 0 0
T36 40072 40068 0 0
T37 2 0 0 0
T38 2 0 0 0
T39 0 20 0 0
T60 0 8 0 0
T66 0 6 0 0
T67 0 4 0 0
T68 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 62845580 62844356 0 0
T1 211817 211815 0 0
T2 84425 84423 0 0
T3 242219 242215 0 0
T4 606425 606421 0 0
T5 0 6 0 0
T8 23334 23330 0 0
T9 0 6 0 0
T11 3112 3108 0 0
T16 9557 9553 0 0
T17 224448 224444 0 0
T35 6200 6196 0 0
T36 99646 99642 0 0
T37 2 0 0 0
T38 2 0 0 0
T39 0 20 0 0
T60 0 8 0 0
T66 0 6 0 0
T67 0 4 0 0
T68 0 10 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2939861 2939664 0 0
selKnown1 56515670 56515473 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2939861 2939664 0 0
T1 15767 15766 0 0
T2 22991 22990 0 0
T3 8988 8987 0 0
T4 17043 17042 0 0
T8 1697 1696 0 0
T11 553 552 0 0
T16 417 416 0 0
T17 21916 21915 0 0
T35 112 111 0 0
T36 20035 20034 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 56515670 56515473 0 0
T1 196050 196049 0 0
T2 61434 61433 0 0
T3 233225 233224 0 0
T4 589374 589373 0 0
T8 21635 21634 0 0
T11 2557 2556 0 0
T16 9138 9137 0 0
T17 202524 202523 0 0
T35 6086 6085 0 0
T36 79609 79608 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 511 314 0 0
selKnown1 458 261 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 511 314 0 0
T3 3 2 0 0
T4 4 3 0 0
T5 0 9 0 0
T8 1 0 0 0
T9 0 3 0 0
T11 1 0 0 0
T16 1 0 0 0
T17 4 3 0 0
T35 1 0 0 0
T36 1 0 0 0
T37 1 0 0 0
T38 1 0 0 0
T39 0 10 0 0
T60 0 4 0 0
T66 0 3 0 0
T67 0 2 0 0
T68 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 458 261 0 0
T3 3 2 0 0
T4 4 3 0 0
T5 0 3 0 0
T8 1 0 0 0
T9 0 3 0 0
T11 1 0 0 0
T16 1 0 0 0
T17 4 3 0 0
T35 1 0 0 0
T36 1 0 0 0
T37 1 0 0 0
T38 1 0 0 0
T39 0 10 0 0
T60 0 4 0 0
T66 0 3 0 0
T67 0 2 0 0
T68 0 5 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6327830 6327415 0 0
selKnown1 6327830 6327415 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6327830 6327415 0 0
T1 15767 15766 0 0
T2 22991 22990 0 0
T3 8988 8987 0 0
T4 17043 17042 0 0
T8 1697 1696 0 0
T11 553 552 0 0
T16 417 416 0 0
T17 21916 21915 0 0
T35 112 111 0 0
T36 20035 20034 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6327830 6327415 0 0
T1 15767 15766 0 0
T2 22991 22990 0 0
T3 8988 8987 0 0
T4 17043 17042 0 0
T8 1697 1696 0 0
T11 553 552 0 0
T16 417 416 0 0
T17 21916 21915 0 0
T35 112 111 0 0
T36 20035 20034 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1856 1441 0 0
selKnown1 1622 1207 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1856 1441 0 0
T3 3 2 0 0
T4 4 3 0 0
T5 0 9 0 0
T8 1 0 0 0
T9 0 5 0 0
T11 1 0 0 0
T16 1 0 0 0
T17 4 3 0 0
T35 1 0 0 0
T36 1 0 0 0
T37 1 0 0 0
T38 1 0 0 0
T39 0 10 0 0
T60 0 4 0 0
T66 0 3 0 0
T67 0 2 0 0
T68 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1622 1207 0 0
T3 3 2 0 0
T4 4 3 0 0
T5 0 3 0 0
T8 1 0 0 0
T9 0 3 0 0
T11 1 0 0 0
T16 1 0 0 0
T17 4 3 0 0
T35 1 0 0 0
T36 1 0 0 0
T37 1 0 0 0
T38 1 0 0 0
T39 0 10 0 0
T60 0 4 0 0
T66 0 3 0 0
T67 0 2 0 0
T68 0 5 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%