SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 197 | 197 | 0 | 0 |
OutputsKnown_A | 56515670 | 56484786 | 0 | 0 |
gen_no_flops.OutputDelay_A | 56515670 | 56484786 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 197 | 197 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56484786 | 0 | 0 |
T1 | 196050 | 195987 | 0 | 0 |
T2 | 61434 | 61373 | 0 | 0 |
T3 | 233225 | 233039 | 0 | 0 |
T4 | 589374 | 589052 | 0 | 0 |
T8 | 21635 | 21574 | 0 | 0 |
T11 | 2557 | 2491 | 0 | 0 |
T16 | 9138 | 9088 | 0 | 0 |
T17 | 202524 | 202254 | 0 | 0 |
T35 | 6086 | 6008 | 0 | 0 |
T36 | 79609 | 79552 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56484786 | 0 | 0 |
T1 | 196050 | 195987 | 0 | 0 |
T2 | 61434 | 61373 | 0 | 0 |
T3 | 233225 | 233039 | 0 | 0 |
T4 | 589374 | 589052 | 0 | 0 |
T8 | 21635 | 21574 | 0 | 0 |
T11 | 2557 | 2491 | 0 | 0 |
T16 | 9138 | 9088 | 0 | 0 |
T17 | 202524 | 202254 | 0 | 0 |
T35 | 6086 | 6008 | 0 | 0 |
T36 | 79609 | 79552 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |