SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
58.07 | 78.43 | 66.67 | 28.57 | 66.67 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.58 | 96.08 | 77.78 | 85.71 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1182 | 1182 | 0 | 0 |
OutputsKnown_A | 339094020 | 338908716 | 0 | 0 |
gen_flops.OutputDelay_A | 169547010 | 169450236 | 0 | 1773 |
gen_no_flops.OutputDelay_A | 169547010 | 169454358 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1182 | 1182 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T11 | 6 | 6 | 0 | 0 |
T16 | 6 | 6 | 0 | 0 |
T17 | 6 | 6 | 0 | 0 |
T35 | 6 | 6 | 0 | 0 |
T36 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 339094020 | 338908716 | 0 | 0 |
T1 | 1176300 | 1175922 | 0 | 0 |
T2 | 368604 | 368238 | 0 | 0 |
T3 | 1399350 | 1398234 | 0 | 0 |
T4 | 3536244 | 3534312 | 0 | 0 |
T8 | 129810 | 129444 | 0 | 0 |
T11 | 15342 | 14946 | 0 | 0 |
T16 | 54828 | 54528 | 0 | 0 |
T17 | 1215144 | 1213524 | 0 | 0 |
T35 | 36516 | 36048 | 0 | 0 |
T36 | 477654 | 477312 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169547010 | 169450236 | 0 | 1773 |
T1 | 588150 | 587952 | 0 | 9 |
T2 | 184302 | 184110 | 0 | 9 |
T3 | 699675 | 699090 | 0 | 9 |
T4 | 1768122 | 1767120 | 0 | 9 |
T8 | 64905 | 64713 | 0 | 9 |
T11 | 7671 | 7464 | 0 | 9 |
T16 | 27414 | 27255 | 0 | 9 |
T17 | 607572 | 606726 | 0 | 9 |
T35 | 18258 | 18015 | 0 | 9 |
T36 | 238827 | 238647 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 169547010 | 169454358 | 0 | 0 |
T1 | 588150 | 587961 | 0 | 0 |
T2 | 184302 | 184119 | 0 | 0 |
T3 | 699675 | 699117 | 0 | 0 |
T4 | 1768122 | 1767156 | 0 | 0 |
T8 | 64905 | 64722 | 0 | 0 |
T11 | 7671 | 7473 | 0 | 0 |
T16 | 27414 | 27264 | 0 | 0 |
T17 | 607572 | 606762 | 0 | 0 |
T35 | 18258 | 18024 | 0 | 0 |
T36 | 238827 | 238656 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 197 | 197 | 0 | 0 |
OutputsKnown_A | 56515670 | 56484786 | 0 | 0 |
gen_flops.OutputDelay_A | 56515670 | 56483412 | 0 | 591 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 197 | 197 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56484786 | 0 | 0 |
T1 | 196050 | 195987 | 0 | 0 |
T2 | 61434 | 61373 | 0 | 0 |
T3 | 233225 | 233039 | 0 | 0 |
T4 | 589374 | 589052 | 0 | 0 |
T8 | 21635 | 21574 | 0 | 0 |
T11 | 2557 | 2491 | 0 | 0 |
T16 | 9138 | 9088 | 0 | 0 |
T17 | 202524 | 202254 | 0 | 0 |
T35 | 6086 | 6008 | 0 | 0 |
T36 | 79609 | 79552 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56483412 | 0 | 591 |
T1 | 196050 | 195984 | 0 | 3 |
T2 | 61434 | 61370 | 0 | 3 |
T3 | 233225 | 233030 | 0 | 3 |
T4 | 589374 | 589040 | 0 | 3 |
T8 | 21635 | 21571 | 0 | 3 |
T11 | 2557 | 2488 | 0 | 3 |
T16 | 9138 | 9085 | 0 | 3 |
T17 | 202524 | 202242 | 0 | 3 |
T35 | 6086 | 6005 | 0 | 3 |
T36 | 79609 | 79549 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 197 | 197 | 0 | 0 |
OutputsKnown_A | 56515670 | 56484786 | 0 | 0 |
gen_flops.OutputDelay_A | 56515670 | 56483412 | 0 | 591 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 197 | 197 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56484786 | 0 | 0 |
T1 | 196050 | 195987 | 0 | 0 |
T2 | 61434 | 61373 | 0 | 0 |
T3 | 233225 | 233039 | 0 | 0 |
T4 | 589374 | 589052 | 0 | 0 |
T8 | 21635 | 21574 | 0 | 0 |
T11 | 2557 | 2491 | 0 | 0 |
T16 | 9138 | 9088 | 0 | 0 |
T17 | 202524 | 202254 | 0 | 0 |
T35 | 6086 | 6008 | 0 | 0 |
T36 | 79609 | 79552 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56483412 | 0 | 591 |
T1 | 196050 | 195984 | 0 | 3 |
T2 | 61434 | 61370 | 0 | 3 |
T3 | 233225 | 233030 | 0 | 3 |
T4 | 589374 | 589040 | 0 | 3 |
T8 | 21635 | 21571 | 0 | 3 |
T11 | 2557 | 2488 | 0 | 3 |
T16 | 9138 | 9085 | 0 | 3 |
T17 | 202524 | 202242 | 0 | 3 |
T35 | 6086 | 6005 | 0 | 3 |
T36 | 79609 | 79549 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 197 | 197 | 0 | 0 |
OutputsKnown_A | 56515670 | 56484786 | 0 | 0 |
gen_no_flops.OutputDelay_A | 56515670 | 56484786 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 197 | 197 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56484786 | 0 | 0 |
T1 | 196050 | 195987 | 0 | 0 |
T2 | 61434 | 61373 | 0 | 0 |
T3 | 233225 | 233039 | 0 | 0 |
T4 | 589374 | 589052 | 0 | 0 |
T8 | 21635 | 21574 | 0 | 0 |
T11 | 2557 | 2491 | 0 | 0 |
T16 | 9138 | 9088 | 0 | 0 |
T17 | 202524 | 202254 | 0 | 0 |
T35 | 6086 | 6008 | 0 | 0 |
T36 | 79609 | 79552 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56484786 | 0 | 0 |
T1 | 196050 | 195987 | 0 | 0 |
T2 | 61434 | 61373 | 0 | 0 |
T3 | 233225 | 233039 | 0 | 0 |
T4 | 589374 | 589052 | 0 | 0 |
T8 | 21635 | 21574 | 0 | 0 |
T11 | 2557 | 2491 | 0 | 0 |
T16 | 9138 | 9088 | 0 | 0 |
T17 | 202524 | 202254 | 0 | 0 |
T35 | 6086 | 6008 | 0 | 0 |
T36 | 79609 | 79552 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 197 | 197 | 0 | 0 |
OutputsKnown_A | 56515670 | 56484786 | 0 | 0 |
gen_flops.OutputDelay_A | 56515670 | 56483412 | 0 | 591 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 197 | 197 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56484786 | 0 | 0 |
T1 | 196050 | 195987 | 0 | 0 |
T2 | 61434 | 61373 | 0 | 0 |
T3 | 233225 | 233039 | 0 | 0 |
T4 | 589374 | 589052 | 0 | 0 |
T8 | 21635 | 21574 | 0 | 0 |
T11 | 2557 | 2491 | 0 | 0 |
T16 | 9138 | 9088 | 0 | 0 |
T17 | 202524 | 202254 | 0 | 0 |
T35 | 6086 | 6008 | 0 | 0 |
T36 | 79609 | 79552 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56483412 | 0 | 591 |
T1 | 196050 | 195984 | 0 | 3 |
T2 | 61434 | 61370 | 0 | 3 |
T3 | 233225 | 233030 | 0 | 3 |
T4 | 589374 | 589040 | 0 | 3 |
T8 | 21635 | 21571 | 0 | 3 |
T11 | 2557 | 2488 | 0 | 3 |
T16 | 9138 | 9085 | 0 | 3 |
T17 | 202524 | 202242 | 0 | 3 |
T35 | 6086 | 6005 | 0 | 3 |
T36 | 79609 | 79549 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 197 | 197 | 0 | 0 |
OutputsKnown_A | 56515670 | 56484786 | 0 | 0 |
gen_no_flops.OutputDelay_A | 56515670 | 56484786 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 197 | 197 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56484786 | 0 | 0 |
T1 | 196050 | 195987 | 0 | 0 |
T2 | 61434 | 61373 | 0 | 0 |
T3 | 233225 | 233039 | 0 | 0 |
T4 | 589374 | 589052 | 0 | 0 |
T8 | 21635 | 21574 | 0 | 0 |
T11 | 2557 | 2491 | 0 | 0 |
T16 | 9138 | 9088 | 0 | 0 |
T17 | 202524 | 202254 | 0 | 0 |
T35 | 6086 | 6008 | 0 | 0 |
T36 | 79609 | 79552 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56484786 | 0 | 0 |
T1 | 196050 | 195987 | 0 | 0 |
T2 | 61434 | 61373 | 0 | 0 |
T3 | 233225 | 233039 | 0 | 0 |
T4 | 589374 | 589052 | 0 | 0 |
T8 | 21635 | 21574 | 0 | 0 |
T11 | 2557 | 2491 | 0 | 0 |
T16 | 9138 | 9088 | 0 | 0 |
T17 | 202524 | 202254 | 0 | 0 |
T35 | 6086 | 6008 | 0 | 0 |
T36 | 79609 | 79552 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 197 | 197 | 0 | 0 |
OutputsKnown_A | 56515670 | 56484786 | 0 | 0 |
gen_no_flops.OutputDelay_A | 56515670 | 56484786 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 197 | 197 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T36 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56484786 | 0 | 0 |
T1 | 196050 | 195987 | 0 | 0 |
T2 | 61434 | 61373 | 0 | 0 |
T3 | 233225 | 233039 | 0 | 0 |
T4 | 589374 | 589052 | 0 | 0 |
T8 | 21635 | 21574 | 0 | 0 |
T11 | 2557 | 2491 | 0 | 0 |
T16 | 9138 | 9088 | 0 | 0 |
T17 | 202524 | 202254 | 0 | 0 |
T35 | 6086 | 6008 | 0 | 0 |
T36 | 79609 | 79552 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56515670 | 56484786 | 0 | 0 |
T1 | 196050 | 195987 | 0 | 0 |
T2 | 61434 | 61373 | 0 | 0 |
T3 | 233225 | 233039 | 0 | 0 |
T4 | 589374 | 589052 | 0 | 0 |
T8 | 21635 | 21574 | 0 | 0 |
T11 | 2557 | 2491 | 0 | 0 |
T16 | 9138 | 9088 | 0 | 0 |
T17 | 202524 | 202254 | 0 | 0 |
T35 | 6086 | 6008 | 0 | 0 |
T36 | 79609 | 79552 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |