Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	188436	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	537818	1		T6	6		T5	2		T7	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	440280	1		T7	10		T20	4		T48	10
values[0x0]	138658	1		T6	11		T5	1		T7	1
values[0x1]	147316	1		T6	9		T5	1		T9	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142577	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	583677	1		T6	8		T5	2		T7	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2838	1		T11	1		T139	1		T140	1
valid_sources[0x01]	2382	1		T141	1		T140	2		T59	3
valid_sources[0x02]	2878	1		T9	1		T141	1		T59	4
valid_sources[0x03]	2914	1		T18	1		T142	1		T39	1
valid_sources[0x04]	2583	1		T8	1		T141	2		T59	3
valid_sources[0x05]	2814	1		T11	2		T27	2		T142	1
valid_sources[0x06]	2756	1		T139	1		T59	5		T56	2
valid_sources[0x07]	2583	1		T8	2		T143	1		T141	2
valid_sources[0x08]	3364	1		T144	16		T59	6		T56	2
valid_sources[0x09]	2744	1		T9	1		T18	1		T139	1
valid_sources[0x0a]	2568	1		T11	1		T27	2		T141	1
valid_sources[0x0b]	2785	1		T8	1		T27	2		T140	2
valid_sources[0x0c]	2735	1		T8	1		T27	1		T140	4
valid_sources[0x0d]	3011	1		T27	1		T141	1		T59	5
valid_sources[0x0e]	3007	1		T8	2		T143	1		T139	1
valid_sources[0x0f]	2425	1		T39	1		T59	8		T56	6
valid_sources[0x10]	2371	1		T27	1		T41	5		T139	2
valid_sources[0x11]	3308	1		T59	10		T56	2		T57	2
valid_sources[0x12]	2688	1		T9	2		T145	1		T146	1
valid_sources[0x13]	2515	1		T142	1		T59	1		T56	4
valid_sources[0x14]	2527	1		T6	1		T8	1		T142	1
valid_sources[0x15]	2667	1		T141	1		T59	6		T56	3
valid_sources[0x16]	2683	1		T8	2		T18	1		T139	1
valid_sources[0x17]	2949	1		T39	1		T59	2		T56	3
valid_sources[0x18]	3701	1		T59	4		T56	5		T57	2
valid_sources[0x19]	2717	1		T8	1		T11	1		T21	1
valid_sources[0x1a]	6445	1		T11	1		T17	12		T41	1
valid_sources[0x1b]	3044	1		T8	1		T11	2		T21	3
valid_sources[0x1c]	2732	1		T9	2		T8	1		T39	1
valid_sources[0x1d]	3108	1		T143	2		T139	1		T59	1
valid_sources[0x1e]	2531	1		T8	1		T141	1		T59	2
valid_sources[0x1f]	2836	1		T9	1		T39	1		T59	4
valid_sources[0x20]	2514	1		T8	1		T27	1		T142	1
valid_sources[0x21]	2787	1		T139	1		T59	1		T57	3
valid_sources[0x22]	2471	1		T143	1		T139	1		T59	7
valid_sources[0x23]	2265	1		T141	1		T43	2		T59	1
valid_sources[0x24]	2404	1		T8	1		T142	1		T141	1
valid_sources[0x25]	2525	1		T11	2		T141	2		T139	2
valid_sources[0x26]	3117	1		T8	1		T10	1		T39	3
valid_sources[0x27]	3078	1		T56	1		T76	11		T52	21
valid_sources[0x28]	2731	1		T39	2		T140	1		T59	5
valid_sources[0x29]	3408	1		T11	1		T139	1		T59	9
valid_sources[0x2a]	2330	1		T142	1		T39	2		T59	4
valid_sources[0x2b]	3045	1		T9	1		T86	1		T144	3
valid_sources[0x2c]	3156	1		T11	2		T18	1		T139	1
valid_sources[0x2d]	2599	1		T8	1		T141	1		T139	1
valid_sources[0x2e]	2876	1		T142	2		T144	9		T139	1
valid_sources[0x2f]	2743	1		T139	1		T59	3		T57	6
valid_sources[0x30]	3130	1		T11	1		T142	1		T139	1
valid_sources[0x31]	2484	1		T9	1		T86	6		T142	1
valid_sources[0x32]	2810	1		T142	1		T39	1		T141	1
valid_sources[0x33]	2847	1		T48	11		T21	2		T59	1
valid_sources[0x34]	2752	1		T8	1		T142	1		T141	1
valid_sources[0x35]	2536	1		T39	3		T139	1		T56	1
valid_sources[0x36]	2342	1		T9	1		T39	1		T59	4
valid_sources[0x37]	2762	1		T86	2		T139	1		T59	6
valid_sources[0x38]	2713	1		T59	2		T56	1		T57	2
valid_sources[0x39]	2726	1		T11	2		T142	1		T144	3
valid_sources[0x3a]	3583	1		T8	1		T11	1		T27	2
valid_sources[0x3b]	2936	1		T142	1		T139	1		T59	7
valid_sources[0x3c]	2643	1		T9	1		T8	1		T139	1
valid_sources[0x3d]	3365	1		T11	2		T31	73		T141	1
valid_sources[0x3e]	3312	1		T141	1		T59	7		T56	6
valid_sources[0x3f]	3066	1		T21	1		T42	93		T141	1
valid_sources[0x40]	2743	1		T8	1		T59	5		T56	3
valid_sources[0x41]	2933	1		T9	1		T11	1		T28	46
valid_sources[0x42]	2502	1		T142	1		T59	7		T56	2
valid_sources[0x43]	3102	1		T139	1		T59	4		T56	2
valid_sources[0x44]	2597	1		T8	1		T56	3		T76	3
valid_sources[0x45]	2772	1		T145	1		T139	1		T59	1
valid_sources[0x46]	2650	1		T143	1		T59	9		T56	2
valid_sources[0x47]	2862	1		T9	1		T141	1		T59	1
valid_sources[0x48]	2389	1		T142	2		T139	1		T59	7
valid_sources[0x49]	2770	1		T9	2		T8	3		T142	1
valid_sources[0x4a]	2566	1		T59	11		T56	2		T57	4
valid_sources[0x4b]	2423	1		T142	1		T39	1		T56	4
valid_sources[0x4c]	2501	1		T142	1		T139	2		T59	4
valid_sources[0x4d]	3232	1		T20	8		T141	1		T139	1
valid_sources[0x4e]	2705	1		T8	1		T11	1		T59	5
valid_sources[0x4f]	2716	1		T11	2		T142	1		T39	1
valid_sources[0x50]	2967	1		T8	1		T12	65		T47	3
valid_sources[0x51]	2970	1		T142	1		T59	4		T56	2
valid_sources[0x52]	2718	1		T18	1		T143	1		T39	1
valid_sources[0x53]	2923	1		T11	1		T142	1		T141	1
valid_sources[0x54]	2694	1		T9	2		T142	1		T141	1
valid_sources[0x55]	3552	1		T11	1		T142	1		T59	3
valid_sources[0x56]	2765	1		T39	1		T144	2		T59	2
valid_sources[0x57]	2610	1		T8	1		T143	1		T141	1
valid_sources[0x58]	2985	1		T6	1		T39	2		T141	1
valid_sources[0x59]	2805	1		T11	1		T18	1		T142	1
valid_sources[0x5a]	2757	1		T6	1		T5	1		T143	1
valid_sources[0x5b]	2631	1		T6	2		T8	1		T141	1
valid_sources[0x5c]	2701	1		T6	2		T9	1		T143	1
valid_sources[0x5d]	2697	1		T59	10		T57	1		T58	15
valid_sources[0x5e]	2818	1		T9	1		T56	3		T57	6
valid_sources[0x5f]	2795	1		T139	1		T59	2		T56	2
valid_sources[0x60]	3020	1		T8	1		T143	1		T146	1
valid_sources[0x61]	2400	1		T39	1		T59	1		T56	5
valid_sources[0x62]	2537	1		T11	1		T142	1		T39	2
valid_sources[0x63]	2557	1		T8	1		T11	2		T59	4
valid_sources[0x64]	3781	1		T9	1		T141	1		T59	2
valid_sources[0x65]	2798	1		T11	1		T143	1		T142	1
valid_sources[0x66]	2925	1		T142	1		T59	1		T56	6
valid_sources[0x67]	2528	1		T9	1		T11	1		T59	3
valid_sources[0x68]	2340	1		T8	1		T59	14		T56	2
valid_sources[0x69]	2341	1		T142	1		T59	7		T56	3
valid_sources[0x6a]	2902	1		T11	3		T143	1		T39	2
valid_sources[0x6b]	2665	1		T14	1		T139	1		T59	4
valid_sources[0x6c]	3219	1		T141	1		T139	2		T59	15
valid_sources[0x6d]	3043	1		T11	1		T140	6		T59	9
valid_sources[0x6e]	2440	1		T47	1		T59	1		T56	3
valid_sources[0x6f]	2379	1		T6	1		T11	1		T39	1
valid_sources[0x70]	2426	1		T6	1		T143	1		T141	2
valid_sources[0x71]	2396	1		T59	4		T56	4		T57	4
valid_sources[0x72]	2384	1		T9	1		T59	1		T56	3
valid_sources[0x73]	2644	1		T11	1		T143	3		T56	1
valid_sources[0x74]	3007	1		T140	2		T59	5		T56	3
valid_sources[0x75]	2867	1		T139	1		T140	2		T59	10
valid_sources[0x76]	2600	1		T11	1		T39	1		T141	1
valid_sources[0x77]	3691	1		T6	1		T14	1		T39	4
valid_sources[0x78]	2722	1		T59	7		T56	1		T57	6
valid_sources[0x79]	2810	1		T9	1		T143	1		T147	10
valid_sources[0x7a]	3088	1		T143	2		T142	2		T59	7
valid_sources[0x7b]	2478	1		T8	2		T143	2		T59	4
valid_sources[0x7c]	2458	1		T9	1		T56	3		T52	24
valid_sources[0x7d]	2590	1		T9	1		T29	2		T59	2
valid_sources[0x7e]	3529	1		T59	7		T56	3		T57	4
valid_sources[0x7f]	2590	1		T11	1		T59	2		T56	3
valid_sources[0x80]	2909	1		T21	9		T141	1		T59	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

265554

1

T7

3

T20

1

T48

6

values[0x0]

all_enables

biggest_size

136298

1

T6

4

T5

1

T7

1

values[0x1]

all_enables

biggest_size

135966

1

T6

2

T5

1

T9

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4495	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	28387	1		T3	4		T33	2		T61	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10776	1		T59	6		T56	6		T57	11
values[0x0]	10799	1		T3	8		T32	2		T33	7
values[0x1]	11307	1		T3	6		T32	5		T33	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3373	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	29509	1		T3	4		T32	1		T33	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	91	1		T148	1		T149	1		T52	12
valid_sources[0x01]	180	1		T150	2		T76	1		T52	20
valid_sources[0x02]	147	1		T52	10		T53	35		T97	2
valid_sources[0x03]	90	1		T52	3		T53	10		T151	3
valid_sources[0x04]	80	1		T55	4		T150	1		T52	11
valid_sources[0x05]	120	1		T148	2		T52	12		T78	1
valid_sources[0x06]	205	1		T150	1		T76	1		T52	16
valid_sources[0x07]	148	1		T152	1		T153	1		T149	1
valid_sources[0x08]	137	1		T154	3		T155	2		T56	1
valid_sources[0x09]	110	1		T76	1		T52	17		T53	9
valid_sources[0x0a]	97	1		T52	6		T156	3		T157	2
valid_sources[0x0b]	103	1		T76	1		T52	19		T53	1
valid_sources[0x0c]	124	1		T52	7		T53	27		T78	8
valid_sources[0x0d]	67	1		T158	3		T52	14		T78	1
valid_sources[0x0e]	94	1		T124	1		T159	1		T52	2
valid_sources[0x0f]	145	1		T76	1		T52	16		T53	2
valid_sources[0x10]	102	1		T160	3		T52	14		T53	13
valid_sources[0x11]	70	1		T161	1		T52	5		T53	4
valid_sources[0x12]	113	1		T158	1		T76	1		T52	2
valid_sources[0x13]	128	1		T150	1		T148	1		T76	1
valid_sources[0x14]	117	1		T148	1		T76	1		T52	13
valid_sources[0x15]	94	1		T52	9		T53	3		T78	2
valid_sources[0x16]	110	1		T52	19		T53	3		T78	2
valid_sources[0x17]	162	1		T162	1		T52	9		T53	1
valid_sources[0x18]	84	1		T163	1		T76	1		T52	12
valid_sources[0x19]	126	1		T80	1		T164	1		T159	1
valid_sources[0x1a]	86	1		T76	1		T52	6		T78	6
valid_sources[0x1b]	101	1		T76	1		T52	18		T53	1
valid_sources[0x1c]	121	1		T165	3		T76	1		T52	8
valid_sources[0x1d]	142	1		T124	1		T76	1		T52	3
valid_sources[0x1e]	241	1		T76	1		T52	6		T53	4
valid_sources[0x1f]	151	1		T76	1		T52	8		T53	26
valid_sources[0x20]	81	1		T33	1		T76	1		T52	5
valid_sources[0x21]	71	1		T124	1		T52	5		T78	3
valid_sources[0x22]	109	1		T52	10		T53	5		T78	1
valid_sources[0x23]	127	1		T3	4		T129	14		T158	1
valid_sources[0x24]	140	1		T155	1		T76	1		T52	7
valid_sources[0x25]	288	1		T61	6		T76	3		T52	15
valid_sources[0x26]	83	1		T152	1		T159	1		T57	1
valid_sources[0x27]	111	1		T80	1		T155	1		T52	13
valid_sources[0x28]	99	1		T166	2		T52	15		T53	3
valid_sources[0x29]	98	1		T167	5		T162	1		T52	3
valid_sources[0x2a]	131	1		T168	5		T152	1		T169	5
valid_sources[0x2b]	95	1		T76	3		T52	14		T53	11
valid_sources[0x2c]	156	1		T52	18		T53	8		T83	4
valid_sources[0x2d]	83	1		T57	1		T52	7		T83	2
valid_sources[0x2e]	207	1		T124	1		T152	1		T52	5
valid_sources[0x2f]	134	1		T158	1		T76	3		T52	6
valid_sources[0x30]	107	1		T170	1		T76	1		T52	6
valid_sources[0x31]	88	1		T82	1		T52	5		T156	1
valid_sources[0x32]	346	1		T170	1		T159	1		T162	1
valid_sources[0x33]	95	1		T52	18		T53	3		T78	1
valid_sources[0x34]	104	1		T33	8		T52	10		T53	6
valid_sources[0x35]	87	1		T163	1		T161	2		T150	1
valid_sources[0x36]	123	1		T60	1		T152	1		T52	8
valid_sources[0x37]	122	1		T148	1		T52	13		T78	1
valid_sources[0x38]	104	1		T76	4		T52	21		T151	5
valid_sources[0x39]	165	1		T162	1		T52	5		T53	28
valid_sources[0x3a]	88	1		T152	1		T76	3		T52	7
valid_sources[0x3b]	90	1		T52	14		T53	1		T78	4
valid_sources[0x3c]	60	1		T158	1		T52	7		T78	1
valid_sources[0x3d]	76	1		T149	1		T76	1		T52	7
valid_sources[0x3e]	108	1		T171	1		T52	12		T53	13
valid_sources[0x3f]	96	1		T3	1		T52	15		T53	13
valid_sources[0x40]	111	1		T172	8		T170	2		T76	1
valid_sources[0x41]	103	1		T81	1		T148	1		T160	1
valid_sources[0x42]	868	1		T79	9		T76	1		T52	4
valid_sources[0x43]	119	1		T76	1		T52	8		T53	3
valid_sources[0x44]	168	1		T173	1		T57	2		T52	19
valid_sources[0x45]	143	1		T52	17		T53	28		T78	4
valid_sources[0x46]	71	1		T52	11		T53	6		T157	2
valid_sources[0x47]	138	1		T3	1		T152	1		T76	2
valid_sources[0x48]	124	1		T155	1		T153	1		T76	3
valid_sources[0x49]	337	1		T171	1		T174	5		T76	4
valid_sources[0x4a]	462	1		T175	1		T162	1		T76	1
valid_sources[0x4b]	98	1		T52	10		T53	5		T78	2
valid_sources[0x4c]	115	1		T149	1		T171	1		T76	1
valid_sources[0x4d]	95	1		T153	1		T52	10		T53	20
valid_sources[0x4e]	85	1		T52	10		T53	10		T83	1
valid_sources[0x4f]	94	1		T155	1		T52	8		T53	2
valid_sources[0x50]	478	1		T162	1		T59	2		T76	1
valid_sources[0x51]	150	1		T52	6		T53	7		T78	1
valid_sources[0x52]	96	1		T171	1		T52	9		T53	20
valid_sources[0x53]	127	1		T81	2		T170	1		T76	1
valid_sources[0x54]	91	1		T163	1		T76	3		T52	14
valid_sources[0x55]	93	1		T170	1		T52	5		T84	32
valid_sources[0x56]	86	1		T85	2		T57	1		T52	15
valid_sources[0x57]	94	1		T160	1		T52	19		T53	4
valid_sources[0x58]	89	1		T52	9		T53	15		T83	2
valid_sources[0x59]	113	1		T81	1		T124	1		T149	1
valid_sources[0x5a]	87	1		T176	1		T150	1		T76	1
valid_sources[0x5b]	206	1		T58	115		T52	4		T53	5
valid_sources[0x5c]	116	1		T150	1		T52	6		T53	14
valid_sources[0x5d]	87	1		T76	1		T52	5		T53	3
valid_sources[0x5e]	103	1		T52	4		T53	4		T97	3
valid_sources[0x5f]	95	1		T76	1		T52	12		T53	1
valid_sources[0x60]	131	1		T3	1		T61	3		T163	1
valid_sources[0x61]	95	1		T164	3		T52	12		T53	11
valid_sources[0x62]	219	1		T171	1		T57	2		T52	5
valid_sources[0x63]	213	1		T81	1		T52	15		T53	7
valid_sources[0x64]	108	1		T80	1		T52	16		T53	1
valid_sources[0x65]	87	1		T170	1		T52	15		T78	2
valid_sources[0x66]	118	1		T152	1		T76	2		T52	13
valid_sources[0x67]	316	1		T52	3		T53	4		T78	4
valid_sources[0x68]	129	1		T57	2		T76	1		T52	19
valid_sources[0x69]	90	1		T76	1		T52	5		T53	11
valid_sources[0x6a]	94	1		T171	1		T52	4		T78	3
valid_sources[0x6b]	100	1		T161	1		T76	5		T52	7
valid_sources[0x6c]	74	1		T56	1		T52	16		T53	1
valid_sources[0x6d]	109	1		T52	20		T53	6		T78	3
valid_sources[0x6e]	122	1		T76	1		T52	15		T53	18
valid_sources[0x6f]	98	1		T71	5		T162	1		T57	1
valid_sources[0x70]	98	1		T148	1		T59	1		T76	3
valid_sources[0x71]	101	1		T76	1		T52	6		T78	1
valid_sources[0x72]	120	1		T59	1		T57	1		T76	2
valid_sources[0x73]	131	1		T57	1		T52	20		T78	8
valid_sources[0x74]	98	1		T155	1		T162	1		T52	6
valid_sources[0x75]	92	1		T161	1		T52	6		T151	1
valid_sources[0x76]	108	1		T81	2		T149	1		T76	1
valid_sources[0x77]	104	1		T33	2		T76	1		T52	7
valid_sources[0x78]	124	1		T52	13		T53	9		T83	1
valid_sources[0x79]	97	1		T76	1		T52	12		T53	12
valid_sources[0x7a]	79	1		T158	1		T169	9		T52	10
valid_sources[0x7b]	251	1		T76	2		T52	10		T53	28
valid_sources[0x7c]	80	1		T155	1		T76	1		T52	12
valid_sources[0x7d]	118	1		T173	2		T76	2		T52	3
valid_sources[0x7e]	78	1		T52	13		T53	1		T78	1
valid_sources[0x7f]	69	1		T148	1		T52	9		T53	3
valid_sources[0x80]	114	1		T52	10		T53	16		T83	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8417

1

T59

1

T56

4

T57

8

values[0x0]

all_enables

biggest_size

10007

1

T3

4

T33

2

T61

2

values[0x1]

all_enables

biggest_size

9963

1

T60

2

T81

2

T129

3