Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
95.83 95.83 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 95.83 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 260014 1 T6 14 T7 7 T9 35
full_word 540725 1 T6 6 T5 2 T7 4



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 800459 1 T6 20 T5 2 T7 11
auto[TlIntgErrCmd] 93 1 T83 4 T96 3 T128 8
auto[TlIntgErrData] 90 1 T83 4 T96 3 T128 8
auto[TlIntgErrBoth] 97 1 T83 2 T96 4 T128 4



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 443548 1 T7 10 T20 4 T48 10
auto[1] 357191 1 T6 20 T5 2 T7 1



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrCmd]] [full_word] [auto[1]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 177569 1 T7 7 T20 3 T48 4
auto[TlIntgErrNone] partial auto[1] 82179 1 T6 14 T9 35 T8 56
auto[TlIntgErrNone] full_word auto[0] 265858 1 T7 3 T20 1 T48 6
auto[TlIntgErrNone] full_word auto[1] 274853 1 T6 6 T5 2 T7 1
auto[TlIntgErrCmd] partial auto[0] 31 1 T96 1 T128 1 T131 3
auto[TlIntgErrCmd] partial auto[1] 60 1 T83 4 T96 1 T128 7
auto[TlIntgErrCmd] full_word auto[0] 2 1 T96 1 T132 1 - -
auto[TlIntgErrData] partial auto[0] 39 1 T83 3 T128 2 T131 2
auto[TlIntgErrData] partial auto[1] 42 1 T96 2 T128 5 T131 5
auto[TlIntgErrData] full_word auto[0] 6 1 T83 1 T96 1 T131 1
auto[TlIntgErrData] full_word auto[1] 3 1 T128 1 T133 1 T134 1
auto[TlIntgErrBoth] partial auto[0] 41 1 T128 3 T131 4 T126 2
auto[TlIntgErrBoth] partial auto[1] 53 1 T83 2 T96 4 T128 1
auto[TlIntgErrBoth] full_word auto[0] 2 1 T133 1 T135 1 - -
auto[TlIntgErrBoth] full_word auto[1] 1 1 T134 1 - - - -

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%