Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.90 96.97 55.32 84.72 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 143096091 25009 0 0
late_debug_enable_rd_A 143096091 3628 0 0
late_debug_enable_regwen_rd_A 143096091 5173 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 143096091 25009 0 0
T52 556388 2361 0 0
T53 407633 2826 0 0
T56 45845 3 0 0
T57 6756 13 0 0
T58 54809 61 0 0
T76 16206 41 0 0
T77 5156 139 0 0
T78 140020 609 0 0
T83 66248 4 0 0
T84 16035 354 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 143096091 3628 0 0
T52 556388 1031 0 0
T76 16206 64 0 0
T78 140020 241 0 0
T83 66248 51 0 0
T87 7816 4 0 0
T92 247543 105 0 0
T93 9853 4 0 0
T125 27284 209 0 0
T126 42267 48 0 0
T127 161649 63 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 143096091 5173 0 0
T52 556388 855 0 0
T59 20892 4 0 0
T76 16206 54 0 0
T78 140020 193 0 0
T83 66248 37 0 0
T87 7816 7 0 0
T92 247543 129 0 0
T125 27284 194 0 0
T126 42267 48 0 0
T127 161649 80 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%