Unified Coverage Report :: Module :: rv_dm_regs_reg_top

Module : rv_dm_regs_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.19	98.69	98.71	93.55		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.90	96.97	55.32	84.72		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	97.78	100.00		93.33			100.00
u_late_debug_enable	100.00	100.00	100.00			100.00
u_late_debug_enable_regwen	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_regs_reg_top

	Line No.	Total	Covered	Percent
TOTAL		35	35	100.00
ALWAYS	67	4	4	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
ALWAYS	215	4	4	100.00
CONT_ASSIGN	221	1	1	100.00
ALWAYS	225	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
ALWAYS	244	4	4	100.00
ALWAYS	252	5	5	100.00
CONT_ASSIGN	277	0	0
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	286	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
67	1	1
68	1	1
69	1	1
70	1	1
			MISSING_ELSE
76	1	1
88	1	1
89	1	1
117	1	1
118	1	1
136	1	1
150	1	1
184	1	1
215	1	1
216	1	1
217	1	1
218	1	1
221	1	1
225	1	1
232	1	1
234	1	1
235	1	1
237	1	1
238	1	1
240	1	1
244	1	1
245	1	1
246	1	1
247	1	1
252	1	1
253	1	1
255	1	1
259	1	1
263	1	1
277		unreachable
285	1	1
286	1	1

---

Cond Coverage for Module : rv_dm_regs_reg_top

	Total	Covered	Percent
Conditions	56	56	100.00
Logical	56	56	100.00
Non-Logical	0	0
Event	0	0

 LINE       57
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T53,T77
1	1	Covered	T3,T32,T33

 LINE       69
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T49,T50,T51
1	0	Covered	T83,T96,T128

 LINE       76
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T49,T50,T51
0	1	0	Covered	T83,T96,T128
1	0	0	Covered	T49,T50,T51

 LINE       118
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T83,T96,T128
0	1	0	Covered	T57,T52,T53
1	0	0	Covered	T52,T53,T77

 LINE       184
 EXPRESSION (late_debug_enable_we & late_debug_enable_regwen_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T83,T96
1	1	Covered	T59,T56,T57

 LINE       216
 EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_ALERT_TEST_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T3,T4,T32
1	Covered	T1,T3,T4

 LINE       217
 EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_LATE_DEBUG_ENABLE_REGWEN_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T55,T98

 LINE       218
 EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_LATE_DEBUG_ENABLE_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T13,T11

 LINE       221
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T32,T33

 LINE       221
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T32,T33
1	0	Covered	T59,T56,T57

 LINE       225
 EXPRESSION (reg_we & ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))))
             ---1--   ----------------------------------------------------------------2---------------------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T3,T32,T33
1	1	Covered	T57,T52,T53

 LINE       225
 SUB-EXPRESSION ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))))
                 -------------------1-------------------   -------------------2-------------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T3,T4,T32
0	0	1	Covered	T4,T13,T11
0	1	0	Covered	T9,T26,T48
1	0	0	Covered	T1,T4,T5

 LINE       225
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T13
1	0	Covered	T3,T4,T32
1	1	Covered	T1,T4,T5

 LINE       225
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T129,T66
1	1	Covered	T9,T26,T48

 LINE       225
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T35,T55,T130
1	1	Covered	T4,T13,T11

 LINE       232
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T56,T57
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T57,T52,T53
1	1	1	Covered	T3,T32,T33

 LINE       235
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T32,T33
1	0	1	Covered	T4,T9,T13
1	1	0	Covered	T52,T53,T77
1	1	1	Covered	T59,T56,T57

 LINE       238
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T32,T33
1	0	1	Covered	T4,T13,T11
1	1	0	Covered	T52,T53,T84
1	1	1	Covered	T59,T56,T57

---

Branch Coverage for Module : rv_dm_regs_reg_top

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	221	2	2	100.00
IF	67	3	3	100.00
CASE	253	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	221	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T32,T33
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	67	if ((!rst_ni))
-2-:	69	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T49,T50,T51
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T2,T3,T4
addr_hit[2]	Covered	T2,T3,T4
default	Covered	T2,T3,T4

---

Assert Coverage for Module : rv_dm_regs_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	143096091	8474	0	0
reAfterRv	143096091	8474	0	0
rePulse	143096091	4755	0	0
wePulse	143096091	3719	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	143096091	8474	0	0
T3	6321	14	0	0
T4	59549	0	0	0
T5	11281	0	0	0
T6	487708	0	0	0
T7	13747	0	0	0
T9	141895	0	0	0
T13	136750	0	0	0
T26	4888	0	0	0
T32	7778	7	0	0
T33	2737	17	0	0
T55	0	4	0	0
T60	0	9	0	0
T61	0	12	0	0
T79	0	12	0	0
T80	0	4	0	0
T81	0	13	0	0
T82	0	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	143096091	8474	0	0
T3	6321	14	0	0
T4	59549	0	0	0
T5	11281	0	0	0
T6	487708	0	0	0
T7	13747	0	0	0
T9	141895	0	0	0
T13	136750	0	0	0
T26	4888	0	0	0
T32	7778	7	0	0
T33	2737	17	0	0
T55	0	4	0	0
T60	0	9	0	0
T61	0	12	0	0
T79	0	12	0	0
T80	0	4	0	0
T81	0	13	0	0
T82	0	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	143096091	4755	0	0
T52	556388	52	0	0
T53	407633	38	0	0
T56	45845	6	0	0
T57	6756	6	0	0
T58	54809	6	0	0
T59	20892	6	0	0
T76	16206	12	0	0
T77	5156	13	0	0
T83	66248	33	0	0
T84	16035	2	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	143096091	3719	0	0
T3	6321	14	0	0
T4	59549	0	0	0
T5	11281	0	0	0
T6	487708	0	0	0
T7	13747	0	0	0
T9	141895	0	0	0
T13	136750	0	0	0
T26	4888	0	0	0
T32	7778	7	0	0
T33	2737	17	0	0
T55	0	4	0	0
T60	0	9	0	0
T61	0	12	0	0
T79	0	12	0	0
T80	0	4	0	0
T81	0	13	0	0
T82	0	1	0	0