Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9737751 |
9736543 |
0 |
0 |
selKnown1 |
56804658 |
56803450 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9737751 |
9736543 |
0 |
0 |
T1 |
9742 |
9740 |
0 |
0 |
T2 |
23876 |
23874 |
0 |
0 |
T3 |
292 |
290 |
0 |
0 |
T4 |
29552 |
29548 |
0 |
0 |
T5 |
1044 |
1040 |
0 |
0 |
T6 |
10240 |
10236 |
0 |
0 |
T7 |
1218 |
1214 |
0 |
0 |
T8 |
0 |
6 |
0 |
0 |
T9 |
80326 |
80322 |
0 |
0 |
T11 |
0 |
18 |
0 |
0 |
T12 |
0 |
26 |
0 |
0 |
T13 |
2 |
0 |
0 |
0 |
T15 |
0 |
12 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T19 |
0 |
14 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T26 |
2 |
0 |
0 |
0 |
T32 |
248 |
244 |
0 |
0 |
T33 |
302 |
298 |
0 |
0 |
T49 |
0 |
40 |
0 |
0 |
T61 |
2 |
0 |
0 |
0 |
T69 |
0 |
3 |
0 |
0 |
T72 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
56804658 |
56803450 |
0 |
0 |
T1 |
209974 |
209972 |
0 |
0 |
T2 |
365273 |
365271 |
0 |
0 |
T3 |
6467 |
6465 |
0 |
0 |
T4 |
74332 |
74328 |
0 |
0 |
T5 |
11804 |
11800 |
0 |
0 |
T6 |
492829 |
492825 |
0 |
0 |
T7 |
14357 |
14353 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
182059 |
182055 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T13 |
2 |
0 |
0 |
0 |
T15 |
0 |
12 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T26 |
2 |
0 |
0 |
0 |
T32 |
7903 |
7899 |
0 |
0 |
T33 |
2889 |
2885 |
0 |
0 |
T49 |
0 |
40 |
0 |
0 |
T61 |
2 |
0 |
0 |
0 |
T69 |
0 |
6 |
0 |
0 |
T70 |
0 |
6 |
0 |
0 |
T72 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2907858 |
2907665 |
0 |
0 |
selKnown1 |
49975115 |
49974922 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2907858 |
2907665 |
0 |
0 |
T1 |
4871 |
4870 |
0 |
0 |
T2 |
11938 |
11937 |
0 |
0 |
T3 |
146 |
145 |
0 |
0 |
T4 |
14769 |
14768 |
0 |
0 |
T5 |
521 |
520 |
0 |
0 |
T6 |
5119 |
5118 |
0 |
0 |
T7 |
608 |
607 |
0 |
0 |
T9 |
40162 |
40161 |
0 |
0 |
T32 |
123 |
122 |
0 |
0 |
T33 |
150 |
149 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49975115 |
49974922 |
0 |
0 |
T1 |
205103 |
205102 |
0 |
0 |
T2 |
353335 |
353334 |
0 |
0 |
T3 |
6321 |
6320 |
0 |
0 |
T4 |
59549 |
59548 |
0 |
0 |
T5 |
11281 |
11280 |
0 |
0 |
T6 |
487708 |
487707 |
0 |
0 |
T7 |
13747 |
13746 |
0 |
0 |
T9 |
141895 |
141894 |
0 |
0 |
T32 |
7778 |
7777 |
0 |
0 |
T33 |
2737 |
2736 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
529 |
336 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
0 |
13 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T15 |
0 |
6 |
0 |
0 |
T16 |
0 |
3 |
0 |
0 |
T19 |
0 |
7 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T49 |
0 |
20 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |
T69 |
0 |
3 |
0 |
0 |
T72 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
440 |
247 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T15 |
0 |
6 |
0 |
0 |
T16 |
0 |
3 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T49 |
0 |
20 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |
T69 |
0 |
3 |
0 |
0 |
T70 |
0 |
3 |
0 |
0 |
T72 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6827549 |
6827138 |
0 |
0 |
selKnown1 |
6827549 |
6827138 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6827549 |
6827138 |
0 |
0 |
T1 |
4871 |
4870 |
0 |
0 |
T2 |
11938 |
11937 |
0 |
0 |
T3 |
146 |
145 |
0 |
0 |
T4 |
14769 |
14768 |
0 |
0 |
T5 |
521 |
520 |
0 |
0 |
T6 |
5119 |
5118 |
0 |
0 |
T7 |
608 |
607 |
0 |
0 |
T9 |
40162 |
40161 |
0 |
0 |
T32 |
123 |
122 |
0 |
0 |
T33 |
150 |
149 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6827549 |
6827138 |
0 |
0 |
T1 |
4871 |
4870 |
0 |
0 |
T2 |
11938 |
11937 |
0 |
0 |
T3 |
146 |
145 |
0 |
0 |
T4 |
14769 |
14768 |
0 |
0 |
T5 |
521 |
520 |
0 |
0 |
T6 |
5119 |
5118 |
0 |
0 |
T7 |
608 |
607 |
0 |
0 |
T9 |
40162 |
40161 |
0 |
0 |
T32 |
123 |
122 |
0 |
0 |
T33 |
150 |
149 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1815 |
1404 |
0 |
0 |
selKnown1 |
1554 |
1143 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1815 |
1404 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
0 |
13 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T15 |
0 |
6 |
0 |
0 |
T16 |
0 |
3 |
0 |
0 |
T19 |
0 |
7 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T49 |
0 |
20 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |
T72 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1554 |
1143 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
1 |
0 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T15 |
0 |
6 |
0 |
0 |
T16 |
0 |
3 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T49 |
0 |
20 |
0 |
0 |
T61 |
1 |
0 |
0 |
0 |
T69 |
0 |
3 |
0 |
0 |
T70 |
0 |
3 |
0 |
0 |
T72 |
0 |
4 |
0 |
0 |