SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 49975115 | 49945793 | 0 | 0 |
gen_no_flops.OutputDelay_A | 49975115 | 49945793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49945793 | 0 | 0 |
T1 | 205103 | 205051 | 0 | 0 |
T2 | 353335 | 353253 | 0 | 0 |
T3 | 6321 | 6244 | 0 | 0 |
T4 | 59549 | 59091 | 0 | 0 |
T5 | 11281 | 11223 | 0 | 0 |
T6 | 487708 | 487647 | 0 | 0 |
T7 | 13747 | 13692 | 0 | 0 |
T9 | 141895 | 141889 | 0 | 0 |
T32 | 7778 | 7726 | 0 | 0 |
T33 | 2737 | 2682 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49945793 | 0 | 0 |
T1 | 205103 | 205051 | 0 | 0 |
T2 | 353335 | 353253 | 0 | 0 |
T3 | 6321 | 6244 | 0 | 0 |
T4 | 59549 | 59091 | 0 | 0 |
T5 | 11281 | 11223 | 0 | 0 |
T6 | 487708 | 487647 | 0 | 0 |
T7 | 13747 | 13692 | 0 | 0 |
T9 | 141895 | 141889 | 0 | 0 |
T32 | 7778 | 7726 | 0 | 0 |
T33 | 2737 | 2682 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |