SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
84.90 | 96.97 | 55.32 | 84.72 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
58.07 | 78.43 | 66.67 | 28.57 | 66.67 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.58 | 96.08 | 77.78 | 85.71 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1158 | 1158 | 0 | 0 |
OutputsKnown_A | 299850690 | 299674758 | 0 | 0 |
gen_flops.OutputDelay_A | 149925345 | 149833419 | 0 | 1737 |
gen_no_flops.OutputDelay_A | 149925345 | 149837379 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1158 | 1158 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T9 | 6 | 6 | 0 | 0 |
T32 | 6 | 6 | 0 | 0 |
T33 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 299850690 | 299674758 | 0 | 0 |
T1 | 1230618 | 1230306 | 0 | 0 |
T2 | 2120010 | 2119518 | 0 | 0 |
T3 | 37926 | 37464 | 0 | 0 |
T4 | 357294 | 354546 | 0 | 0 |
T5 | 67686 | 67338 | 0 | 0 |
T6 | 2926248 | 2925882 | 0 | 0 |
T7 | 82482 | 82152 | 0 | 0 |
T9 | 851370 | 851334 | 0 | 0 |
T32 | 46668 | 46356 | 0 | 0 |
T33 | 16422 | 16092 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 149925345 | 149833419 | 0 | 1737 |
T1 | 615309 | 615144 | 0 | 9 |
T2 | 1060005 | 1059750 | 0 | 9 |
T3 | 18963 | 18723 | 0 | 9 |
T4 | 178647 | 177210 | 0 | 9 |
T5 | 33843 | 33660 | 0 | 9 |
T6 | 1463124 | 1462932 | 0 | 9 |
T7 | 41241 | 41067 | 0 | 9 |
T9 | 425685 | 425667 | 0 | 9 |
T32 | 23334 | 23169 | 0 | 9 |
T33 | 8211 | 8037 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 149925345 | 149837379 | 0 | 0 |
T1 | 615309 | 615153 | 0 | 0 |
T2 | 1060005 | 1059759 | 0 | 0 |
T3 | 18963 | 18732 | 0 | 0 |
T4 | 178647 | 177273 | 0 | 0 |
T5 | 33843 | 33669 | 0 | 0 |
T6 | 1463124 | 1462941 | 0 | 0 |
T7 | 41241 | 41076 | 0 | 0 |
T9 | 425685 | 425667 | 0 | 0 |
T32 | 23334 | 23178 | 0 | 0 |
T33 | 8211 | 8046 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 49975115 | 49945793 | 0 | 0 |
gen_flops.OutputDelay_A | 49975115 | 49944473 | 0 | 579 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49945793 | 0 | 0 |
T1 | 205103 | 205051 | 0 | 0 |
T2 | 353335 | 353253 | 0 | 0 |
T3 | 6321 | 6244 | 0 | 0 |
T4 | 59549 | 59091 | 0 | 0 |
T5 | 11281 | 11223 | 0 | 0 |
T6 | 487708 | 487647 | 0 | 0 |
T7 | 13747 | 13692 | 0 | 0 |
T9 | 141895 | 141889 | 0 | 0 |
T32 | 7778 | 7726 | 0 | 0 |
T33 | 2737 | 2682 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49944473 | 0 | 579 |
T1 | 205103 | 205048 | 0 | 3 |
T2 | 353335 | 353250 | 0 | 3 |
T3 | 6321 | 6241 | 0 | 3 |
T4 | 59549 | 59070 | 0 | 3 |
T5 | 11281 | 11220 | 0 | 3 |
T6 | 487708 | 487644 | 0 | 3 |
T7 | 13747 | 13689 | 0 | 3 |
T9 | 141895 | 141889 | 0 | 3 |
T32 | 7778 | 7723 | 0 | 3 |
T33 | 2737 | 2679 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 49975115 | 49945793 | 0 | 0 |
gen_flops.OutputDelay_A | 49975115 | 49944473 | 0 | 579 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49945793 | 0 | 0 |
T1 | 205103 | 205051 | 0 | 0 |
T2 | 353335 | 353253 | 0 | 0 |
T3 | 6321 | 6244 | 0 | 0 |
T4 | 59549 | 59091 | 0 | 0 |
T5 | 11281 | 11223 | 0 | 0 |
T6 | 487708 | 487647 | 0 | 0 |
T7 | 13747 | 13692 | 0 | 0 |
T9 | 141895 | 141889 | 0 | 0 |
T32 | 7778 | 7726 | 0 | 0 |
T33 | 2737 | 2682 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49944473 | 0 | 579 |
T1 | 205103 | 205048 | 0 | 3 |
T2 | 353335 | 353250 | 0 | 3 |
T3 | 6321 | 6241 | 0 | 3 |
T4 | 59549 | 59070 | 0 | 3 |
T5 | 11281 | 11220 | 0 | 3 |
T6 | 487708 | 487644 | 0 | 3 |
T7 | 13747 | 13689 | 0 | 3 |
T9 | 141895 | 141889 | 0 | 3 |
T32 | 7778 | 7723 | 0 | 3 |
T33 | 2737 | 2679 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 49975115 | 49945793 | 0 | 0 |
gen_no_flops.OutputDelay_A | 49975115 | 49945793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49945793 | 0 | 0 |
T1 | 205103 | 205051 | 0 | 0 |
T2 | 353335 | 353253 | 0 | 0 |
T3 | 6321 | 6244 | 0 | 0 |
T4 | 59549 | 59091 | 0 | 0 |
T5 | 11281 | 11223 | 0 | 0 |
T6 | 487708 | 487647 | 0 | 0 |
T7 | 13747 | 13692 | 0 | 0 |
T9 | 141895 | 141889 | 0 | 0 |
T32 | 7778 | 7726 | 0 | 0 |
T33 | 2737 | 2682 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49945793 | 0 | 0 |
T1 | 205103 | 205051 | 0 | 0 |
T2 | 353335 | 353253 | 0 | 0 |
T3 | 6321 | 6244 | 0 | 0 |
T4 | 59549 | 59091 | 0 | 0 |
T5 | 11281 | 11223 | 0 | 0 |
T6 | 487708 | 487647 | 0 | 0 |
T7 | 13747 | 13692 | 0 | 0 |
T9 | 141895 | 141889 | 0 | 0 |
T32 | 7778 | 7726 | 0 | 0 |
T33 | 2737 | 2682 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 49975115 | 49945793 | 0 | 0 |
gen_flops.OutputDelay_A | 49975115 | 49944473 | 0 | 579 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49945793 | 0 | 0 |
T1 | 205103 | 205051 | 0 | 0 |
T2 | 353335 | 353253 | 0 | 0 |
T3 | 6321 | 6244 | 0 | 0 |
T4 | 59549 | 59091 | 0 | 0 |
T5 | 11281 | 11223 | 0 | 0 |
T6 | 487708 | 487647 | 0 | 0 |
T7 | 13747 | 13692 | 0 | 0 |
T9 | 141895 | 141889 | 0 | 0 |
T32 | 7778 | 7726 | 0 | 0 |
T33 | 2737 | 2682 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49944473 | 0 | 579 |
T1 | 205103 | 205048 | 0 | 3 |
T2 | 353335 | 353250 | 0 | 3 |
T3 | 6321 | 6241 | 0 | 3 |
T4 | 59549 | 59070 | 0 | 3 |
T5 | 11281 | 11220 | 0 | 3 |
T6 | 487708 | 487644 | 0 | 3 |
T7 | 13747 | 13689 | 0 | 3 |
T9 | 141895 | 141889 | 0 | 3 |
T32 | 7778 | 7723 | 0 | 3 |
T33 | 2737 | 2679 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 49975115 | 49945793 | 0 | 0 |
gen_no_flops.OutputDelay_A | 49975115 | 49945793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49945793 | 0 | 0 |
T1 | 205103 | 205051 | 0 | 0 |
T2 | 353335 | 353253 | 0 | 0 |
T3 | 6321 | 6244 | 0 | 0 |
T4 | 59549 | 59091 | 0 | 0 |
T5 | 11281 | 11223 | 0 | 0 |
T6 | 487708 | 487647 | 0 | 0 |
T7 | 13747 | 13692 | 0 | 0 |
T9 | 141895 | 141889 | 0 | 0 |
T32 | 7778 | 7726 | 0 | 0 |
T33 | 2737 | 2682 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49945793 | 0 | 0 |
T1 | 205103 | 205051 | 0 | 0 |
T2 | 353335 | 353253 | 0 | 0 |
T3 | 6321 | 6244 | 0 | 0 |
T4 | 59549 | 59091 | 0 | 0 |
T5 | 11281 | 11223 | 0 | 0 |
T6 | 487708 | 487647 | 0 | 0 |
T7 | 13747 | 13692 | 0 | 0 |
T9 | 141895 | 141889 | 0 | 0 |
T32 | 7778 | 7726 | 0 | 0 |
T33 | 2737 | 2682 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 193 | 193 | 0 | 0 |
OutputsKnown_A | 49975115 | 49945793 | 0 | 0 |
gen_no_flops.OutputDelay_A | 49975115 | 49945793 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 193 | 193 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49945793 | 0 | 0 |
T1 | 205103 | 205051 | 0 | 0 |
T2 | 353335 | 353253 | 0 | 0 |
T3 | 6321 | 6244 | 0 | 0 |
T4 | 59549 | 59091 | 0 | 0 |
T5 | 11281 | 11223 | 0 | 0 |
T6 | 487708 | 487647 | 0 | 0 |
T7 | 13747 | 13692 | 0 | 0 |
T9 | 141895 | 141889 | 0 | 0 |
T32 | 7778 | 7726 | 0 | 0 |
T33 | 2737 | 2682 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 49975115 | 49945793 | 0 | 0 |
T1 | 205103 | 205051 | 0 | 0 |
T2 | 353335 | 353253 | 0 | 0 |
T3 | 6321 | 6244 | 0 | 0 |
T4 | 59549 | 59091 | 0 | 0 |
T5 | 11281 | 11223 | 0 | 0 |
T6 | 487708 | 487647 | 0 | 0 |
T7 | 13747 | 13692 | 0 | 0 |
T9 | 141895 | 141889 | 0 | 0 |
T32 | 7778 | 7726 | 0 | 0 |
T33 | 2737 | 2682 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |