Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199371	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	553928	1		T1	7		T4	80		T8	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	466061	1		T4	80		T11	6		T32	6
values[0x0]	139944	1		T1	9		T8	5		T5	10
values[0x1]	147294	1		T1	7		T8	3		T5	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151563	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	601736	1		T1	8		T4	80		T8	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3666	1		T18	1		T20	1		T49	10
valid_sources[0x01]	3589	1		T11	1		T49	18		T50	25
valid_sources[0x02]	2444	1		T11	8		T32	1		T49	22
valid_sources[0x03]	2789	1		T11	1		T42	2		T49	29
valid_sources[0x04]	3042	1		T5	2		T7	1		T49	20
valid_sources[0x05]	2803	1		T6	3		T7	1		T48	2
valid_sources[0x06]	2856	1		T7	1		T69	29		T49	17
valid_sources[0x07]	2822	1		T33	2		T19	3		T49	12
valid_sources[0x08]	3267	1		T33	1		T20	1		T49	10
valid_sources[0x09]	2657	1		T33	1		T19	1		T49	20
valid_sources[0x0a]	2541	1		T33	1		T40	1		T49	27
valid_sources[0x0b]	3138	1		T19	1		T49	14		T50	32
valid_sources[0x0c]	2692	1		T33	2		T134	2		T49	37
valid_sources[0x0d]	3170	1		T11	6		T20	3		T135	9
valid_sources[0x0e]	2473	1		T11	2		T136	27		T19	2
valid_sources[0x0f]	2769	1		T6	1		T38	2		T135	3
valid_sources[0x10]	2723	1		T33	1		T49	3		T50	22
valid_sources[0x11]	3380	1		T48	2		T49	17		T50	19
valid_sources[0x12]	3054	1		T5	1		T49	11		T50	6
valid_sources[0x13]	2685	1		T6	3		T137	2		T49	25
valid_sources[0x14]	2643	1		T38	1		T49	18		T50	17
valid_sources[0x15]	2890	1		T135	8		T49	19		T50	18
valid_sources[0x16]	2693	1		T48	1		T20	1		T49	22
valid_sources[0x17]	2508	1		T6	1		T39	9		T19	1
valid_sources[0x18]	2965	1		T19	1		T38	2		T49	19
valid_sources[0x19]	2328	1		T19	1		T49	32		T50	18
valid_sources[0x1a]	3363	1		T7	2		T49	35		T50	17
valid_sources[0x1b]	2571	1		T49	14		T50	35		T51	4
valid_sources[0x1c]	3274	1		T19	1		T20	5		T49	13
valid_sources[0x1d]	2574	1		T6	1		T20	2		T49	24
valid_sources[0x1e]	2831	1		T11	2		T37	24		T33	1
valid_sources[0x1f]	2814	1		T48	1		T49	20		T50	15
valid_sources[0x20]	2980	1		T11	1		T18	1		T49	15
valid_sources[0x21]	3678	1		T18	1		T49	36		T50	22
valid_sources[0x22]	2968	1		T6	1		T32	1		T49	25
valid_sources[0x23]	2943	1		T1	1		T33	1		T19	1
valid_sources[0x24]	2811	1		T11	2		T19	1		T49	17
valid_sources[0x25]	2971	1		T34	2		T19	1		T49	8
valid_sources[0x26]	2811	1		T6	1		T19	1		T49	8
valid_sources[0x27]	3495	1		T49	27		T50	26		T51	7
valid_sources[0x28]	2540	1		T48	1		T19	1		T138	2
valid_sources[0x29]	2753	1		T6	1		T33	1		T48	1
valid_sources[0x2a]	2908	1		T6	1		T34	2		T49	15
valid_sources[0x2b]	2631	1		T49	20		T50	35		T51	3
valid_sources[0x2c]	3811	1		T19	2		T139	29		T49	21
valid_sources[0x2d]	2421	1		T6	1		T11	4		T18	1
valid_sources[0x2e]	2887	1		T140	14		T49	8		T50	13
valid_sources[0x2f]	2905	1		T34	2		T49	17		T50	18
valid_sources[0x30]	2693	1		T49	12		T50	23		T51	3
valid_sources[0x31]	2878	1		T18	1		T33	3		T19	1
valid_sources[0x32]	2563	1		T6	2		T7	1		T19	4
valid_sources[0x33]	3194	1		T6	1		T19	1		T135	14
valid_sources[0x34]	3312	1		T19	1		T40	2		T49	17
valid_sources[0x35]	3342	1		T1	2		T33	1		T49	56
valid_sources[0x36]	2435	1		T1	2		T11	1		T18	1
valid_sources[0x37]	3018	1		T6	1		T11	2		T19	2
valid_sources[0x38]	3356	1		T5	2		T33	1		T49	10
valid_sources[0x39]	3064	1		T18	1		T19	2		T20	1
valid_sources[0x3a]	3075	1		T8	8		T20	1		T135	1
valid_sources[0x3b]	2971	1		T49	11		T50	13		T51	1
valid_sources[0x3c]	3087	1		T6	1		T7	1		T34	2
valid_sources[0x3d]	2733	1		T7	1		T19	2		T20	3
valid_sources[0x3e]	2510	1		T5	1		T18	1		T49	17
valid_sources[0x3f]	2658	1		T11	7		T18	1		T41	4
valid_sources[0x40]	2917	1		T19	1		T20	3		T38	2
valid_sources[0x41]	3260	1		T5	2		T19	1		T49	24
valid_sources[0x42]	2736	1		T49	3		T50	24		T65	14
valid_sources[0x43]	2770	1		T34	1		T19	1		T41	1
valid_sources[0x44]	2947	1		T76	14		T19	1		T49	27
valid_sources[0x45]	2885	1		T19	2		T49	19		T50	31
valid_sources[0x46]	2534	1		T49	33		T50	17		T51	1
valid_sources[0x47]	2516	1		T6	2		T19	1		T38	1
valid_sources[0x48]	3003	1		T33	2		T19	2		T49	10
valid_sources[0x49]	2963	1		T19	1		T140	3		T49	49
valid_sources[0x4a]	2550	1		T11	5		T33	1		T20	5
valid_sources[0x4b]	2591	1		T11	3		T40	1		T49	13
valid_sources[0x4c]	2852	1		T49	23		T50	22		T51	2
valid_sources[0x4d]	2917	1		T33	1		T48	1		T49	21
valid_sources[0x4e]	2715	1		T11	1		T34	2		T49	19
valid_sources[0x4f]	2496	1		T49	43		T50	17		T65	15
valid_sources[0x50]	3227	1		T6	1		T34	1		T18	1
valid_sources[0x51]	2718	1		T49	15		T50	30		T51	2
valid_sources[0x52]	2622	1		T18	1		T19	1		T49	23
valid_sources[0x53]	3071	1		T7	1		T33	1		T20	2
valid_sources[0x54]	2982	1		T6	4		T18	1		T41	1
valid_sources[0x55]	2935	1		T33	1		T19	1		T20	3
valid_sources[0x56]	3176	1		T19	1		T135	2		T49	14
valid_sources[0x57]	3145	1		T6	1		T11	1		T19	2
valid_sources[0x58]	2537	1		T18	1		T33	1		T19	4
valid_sources[0x59]	3171	1		T11	8		T18	1		T33	1
valid_sources[0x5a]	2670	1		T19	2		T49	29		T50	26
valid_sources[0x5b]	3273	1		T6	1		T34	2		T33	3
valid_sources[0x5c]	2847	1		T11	1		T19	1		T42	1
valid_sources[0x5d]	4101	1		T1	1		T18	3		T49	35
valid_sources[0x5e]	2797	1		T19	1		T49	34		T50	18
valid_sources[0x5f]	2561	1		T6	1		T33	1		T49	12
valid_sources[0x60]	2821	1		T34	3		T18	1		T19	1
valid_sources[0x61]	2713	1		T11	2		T18	1		T19	1
valid_sources[0x62]	3104	1		T19	1		T49	21		T50	13
valid_sources[0x63]	3036	1		T7	1		T33	1		T19	1
valid_sources[0x64]	3127	1		T6	1		T33	1		T49	4
valid_sources[0x65]	3104	1		T37	1		T19	2		T134	1
valid_sources[0x66]	2559	1		T7	1		T19	1		T134	1
valid_sources[0x67]	2362	1		T6	1		T141	1		T134	1
valid_sources[0x68]	3226	1		T11	1		T19	1		T49	21
valid_sources[0x69]	2509	1		T49	27		T50	26		T51	1
valid_sources[0x6a]	2728	1		T7	2		T33	3		T40	1
valid_sources[0x6b]	3393	1		T33	1		T19	1		T49	37
valid_sources[0x6c]	2683	1		T49	23		T50	19		T51	4
valid_sources[0x6d]	3067	1		T5	5		T33	1		T49	31
valid_sources[0x6e]	3023	1		T33	2		T19	1		T49	22
valid_sources[0x6f]	2473	1		T19	2		T49	16		T50	26
valid_sources[0x70]	2887	1		T11	1		T19	1		T49	9
valid_sources[0x71]	3162	1		T11	1		T33	1		T49	18
valid_sources[0x72]	2947	1		T11	2		T19	1		T38	1
valid_sources[0x73]	3179	1		T33	1		T49	36		T50	22
valid_sources[0x74]	4162	1		T20	1		T49	18		T50	9
valid_sources[0x75]	2974	1		T18	1		T19	1		T138	8
valid_sources[0x76]	2523	1		T6	1		T40	1		T49	20
valid_sources[0x77]	3297	1		T18	1		T48	1		T19	2
valid_sources[0x78]	2874	1		T5	2		T19	1		T142	20
valid_sources[0x79]	3247	1		T7	1		T49	10		T50	25
valid_sources[0x7a]	3073	1		T11	1		T34	1		T33	1
valid_sources[0x7b]	3161	1		T7	1		T18	1		T37	13
valid_sources[0x7c]	2768	1		T19	1		T49	10		T50	17
valid_sources[0x7d]	3010	1		T33	1		T49	8		T50	16
valid_sources[0x7e]	3711	1		T18	1		T33	1		T49	25
valid_sources[0x7f]	2762	1		T6	1		T32	1		T33	1
valid_sources[0x80]	3150	1		T1	1		T33	5		T135	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

278785

1

T4

80

T11

2

T32

2

values[0x0]

all_enables

biggest_size

137656

1

T1

4

T8

1

T5

4

values[0x1]

all_enables

biggest_size

137487

1

T1

3

T8

1

T5

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5068	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	27772	1		T2	3		T24	1		T25	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11708	1		T49	33		T50	34		T51	34
values[0x0]	10389	1		T2	3		T24	2		T25	3
values[0x1]	10743	1		T2	6		T26	5		T27	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3753	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	29087	1		T2	4		T24	1		T25	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	86	1		T52	1		T143	1		T70	2
valid_sources[0x01]	74	1		T144	1		T145	2		T65	1
valid_sources[0x02]	142	1		T66	1		T117	1		T63	1
valid_sources[0x03]	99	1		T146	11		T147	2		T65	2
valid_sources[0x04]	292	1		T70	3		T46	37		T73	10
valid_sources[0x05]	153	1		T27	1		T72	4		T73	4
valid_sources[0x06]	69	1		T24	2		T67	1		T68	1
valid_sources[0x07]	149	1		T148	12		T81	1		T70	2
valid_sources[0x08]	114	1		T149	1		T65	1		T70	3
valid_sources[0x09]	208	1		T70	1		T46	118		T73	2
valid_sources[0x0a]	90	1		T77	1		T70	6		T87	3
valid_sources[0x0b]	78	1		T150	2		T50	2		T65	1
valid_sources[0x0c]	74	1		T73	9		T87	4		T47	4
valid_sources[0x0d]	79	1		T70	1		T73	7		T87	3
valid_sources[0x0e]	86	1		T151	2		T152	1		T77	2
valid_sources[0x0f]	79	1		T65	1		T63	1		T70	5
valid_sources[0x10]	73	1		T153	1		T65	1		T63	1
valid_sources[0x11]	90	1		T70	2		T46	1		T47	7
valid_sources[0x12]	139	1		T77	3		T70	2		T72	2
valid_sources[0x13]	93	1		T68	2		T154	12		T155	6
valid_sources[0x14]	170	1		T49	2		T70	1		T46	26
valid_sources[0x15]	110	1		T51	2		T81	1		T70	2
valid_sources[0x16]	80	1		T87	2		T47	9		T133	13
valid_sources[0x17]	250	1		T49	5		T63	1		T71	13
valid_sources[0x18]	101	1		T144	1		T156	1		T70	2
valid_sources[0x19]	101	1		T63	2		T73	2		T87	3
valid_sources[0x1a]	135	1		T2	1		T157	1		T81	1
valid_sources[0x1b]	77	1		T158	1		T65	1		T81	2
valid_sources[0x1c]	91	1		T159	4		T63	1		T72	4
valid_sources[0x1d]	83	1		T63	1		T79	1		T70	1
valid_sources[0x1e]	159	1		T50	1		T70	3		T46	38
valid_sources[0x1f]	106	1		T120	2		T73	6		T87	4
valid_sources[0x20]	453	1		T160	2		T49	7		T70	1
valid_sources[0x21]	119	1		T65	1		T70	1		T72	4
valid_sources[0x22]	103	1		T78	1		T81	1		T70	5
valid_sources[0x23]	117	1		T65	1		T73	2		T47	13
valid_sources[0x24]	165	1		T117	2		T150	3		T70	1
valid_sources[0x25]	97	1		T52	1		T150	1		T70	1
valid_sources[0x26]	123	1		T160	1		T65	1		T87	1
valid_sources[0x27]	93	1		T145	1		T160	2		T70	1
valid_sources[0x28]	91	1		T161	1		T162	1		T50	1
valid_sources[0x29]	107	1		T65	1		T70	2		T87	3
valid_sources[0x2a]	129	1		T163	1		T50	2		T63	2
valid_sources[0x2b]	107	1		T152	1		T63	1		T70	1
valid_sources[0x2c]	94	1		T65	1		T78	1		T70	5
valid_sources[0x2d]	93	1		T164	9		T63	2		T73	1
valid_sources[0x2e]	121	1		T145	1		T159	2		T70	1
valid_sources[0x2f]	104	1		T151	2		T70	3		T87	4
valid_sources[0x30]	100	1		T68	2		T153	1		T70	2
valid_sources[0x31]	81	1		T66	2		T70	2		T71	24
valid_sources[0x32]	115	1		T63	1		T72	3		T87	1
valid_sources[0x33]	124	1		T81	1		T70	2		T74	9
valid_sources[0x34]	77	1		T161	1		T87	1		T47	8
valid_sources[0x35]	113	1		T156	1		T49	2		T81	1
valid_sources[0x36]	118	1		T165	16		T65	1		T46	2
valid_sources[0x37]	87	1		T153	3		T65	1		T63	1
valid_sources[0x38]	96	1		T52	2		T147	1		T70	4
valid_sources[0x39]	128	1		T150	5		T166	1		T162	2
valid_sources[0x3a]	225	1		T117	1		T150	2		T160	4
valid_sources[0x3b]	132	1		T63	1		T81	1		T70	1
valid_sources[0x3c]	143	1		T65	1		T70	1		T85	1
valid_sources[0x3d]	150	1		T81	1		T70	1		T87	1
valid_sources[0x3e]	119	1		T68	2		T70	1		T46	2
valid_sources[0x3f]	145	1		T161	1		T120	1		T162	1
valid_sources[0x40]	98	1		T145	1		T63	1		T79	2
valid_sources[0x41]	127	1		T166	3		T50	1		T70	2
valid_sources[0x42]	163	1		T70	2		T46	10		T74	13
valid_sources[0x43]	119	1		T49	9		T65	1		T73	5
valid_sources[0x44]	118	1		T81	1		T87	3		T92	2
valid_sources[0x45]	83	1		T70	1		T46	1		T87	2
valid_sources[0x46]	238	1		T144	1		T117	1		T158	2
valid_sources[0x47]	104	1		T52	1		T150	1		T50	2
valid_sources[0x48]	101	1		T70	1		T73	3		T87	4
valid_sources[0x49]	297	1		T63	1		T70	3		T71	7
valid_sources[0x4a]	410	1		T25	1		T167	4		T160	2
valid_sources[0x4b]	113	1		T157	1		T149	1		T147	1
valid_sources[0x4c]	56	1		T50	1		T46	1		T47	8
valid_sources[0x4d]	165	1		T157	1		T50	1		T65	1
valid_sources[0x4e]	101	1		T168	9		T50	1		T70	1
valid_sources[0x4f]	201	1		T120	1		T65	1		T70	1
valid_sources[0x50]	101	1		T82	7		T47	16		T115	1
valid_sources[0x51]	78	1		T120	1		T163	4		T70	4
valid_sources[0x52]	81	1		T144	1		T50	3		T70	2
valid_sources[0x53]	171	1		T63	1		T70	1		T73	4
valid_sources[0x54]	126	1		T66	1		T63	1		T70	1
valid_sources[0x55]	73	1		T25	1		T50	3		T81	1
valid_sources[0x56]	130	1		T70	1		T46	38		T73	9
valid_sources[0x57]	141	1		T26	7		T81	1		T70	1
valid_sources[0x58]	116	1		T70	1		T85	1		T47	10
valid_sources[0x59]	199	1		T116	4		T169	6		T50	2
valid_sources[0x5a]	93	1		T170	7		T70	5		T47	11
valid_sources[0x5b]	72	1		T147	1		T72	5		T74	2
valid_sources[0x5c]	204	1		T158	1		T120	1		T151	1
valid_sources[0x5d]	148	1		T162	1		T70	3		T46	1
valid_sources[0x5e]	90	1		T147	1		T163	1		T49	4
valid_sources[0x5f]	246	1		T63	1		T81	1		T46	156
valid_sources[0x60]	84	1		T47	6		T171	6		T133	7
valid_sources[0x61]	175	1		T149	1		T63	2		T46	86
valid_sources[0x62]	97	1		T172	2		T82	4		T72	1
valid_sources[0x63]	67	1		T144	1		T120	1		T173	3
valid_sources[0x64]	117	1		T50	1		T70	2		T87	4
valid_sources[0x65]	96	1		T151	1		T174	7		T81	2
valid_sources[0x66]	277	1		T81	1		T70	1		T71	5
valid_sources[0x67]	253	1		T157	2		T172	2		T65	2
valid_sources[0x68]	109	1		T70	1		T72	1		T87	2
valid_sources[0x69]	115	1		T70	2		T72	1		T46	1
valid_sources[0x6a]	313	1		T175	5		T65	1		T70	2
valid_sources[0x6b]	87	1		T120	1		T152	2		T65	1
valid_sources[0x6c]	101	1		T52	2		T66	1		T51	1
valid_sources[0x6d]	130	1		T50	3		T81	1		T85	1
valid_sources[0x6e]	216	1		T50	1		T73	1		T127	3
valid_sources[0x6f]	157	1		T50	2		T73	6		T87	1
valid_sources[0x70]	111	1		T2	3		T70	2		T73	11
valid_sources[0x71]	112	1		T176	2		T65	1		T63	2
valid_sources[0x72]	102	1		T63	1		T70	2		T72	1
valid_sources[0x73]	66	1		T161	1		T78	1		T70	2
valid_sources[0x74]	98	1		T166	1		T50	1		T70	1
valid_sources[0x75]	113	1		T144	1		T63	1		T70	5
valid_sources[0x76]	144	1		T70	1		T72	1		T74	3
valid_sources[0x77]	108	1		T166	1		T70	2		T73	1
valid_sources[0x78]	180	1		T51	33		T65	1		T73	2
valid_sources[0x79]	174	1		T68	4		T150	1		T63	1
valid_sources[0x7a]	109	1		T162	1		T70	5		T71	2
valid_sources[0x7b]	313	1		T172	4		T65	1		T63	1
valid_sources[0x7c]	208	1		T144	1		T46	90		T73	6
valid_sources[0x7d]	127	1		T120	1		T51	31		T70	3
valid_sources[0x7e]	85	1		T144	1		T117	1		T127	3
valid_sources[0x7f]	99	1		T151	3		T167	1		T50	1
valid_sources[0x80]	121	1		T144	1		T80	5		T87	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8752

1

T49

14

T50

13

T51

32

values[0x0]

all_enables

biggest_size

9608

1

T2

2

T24

1

T25

1

values[0x1]

all_enables

biggest_size

9412

1

T2

1

T27

2

T66

1