Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	262249	1		T1	9		T8	6		T5	14
full_word	556636	1		T1	7		T4	80		T8	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	818585	1		T1	16		T4	80		T8	8
auto[TlIntgErrCmd]	90	1		T49	3		T50	4		T65	3
auto[TlIntgErrData]	110	1		T49	1		T50	2		T65	5
auto[TlIntgErrBoth]	100	1		T49	6		T50	4		T65	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	469333	1		T4	80		T11	6		T32	6
auto[1]	349552	1		T1	16		T8	8		T5	20

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	190087	1		T11	4		T32	4		T34	5
auto[TlIntgErrNone]	partial	auto[1]	71880	1		T1	9		T8	6		T5	14
auto[TlIntgErrNone]	full_word	auto[0]	279119	1		T4	80		T11	2		T32	2
auto[TlIntgErrNone]	full_word	auto[1]	277499	1		T1	7		T8	2		T5	6
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T49	1		T50	1		T65	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T49	1		T50	3		T65	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T49	1		T74	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T123	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	50	1		T50	1		T65	1		T72	2
auto[TlIntgErrData]	partial	auto[1]	51	1		T49	1		T50	1		T65	4
auto[TlIntgErrData]	full_word	auto[0]	4	1		T129	1		T130	1		T131	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T72	1		T124	1		T128	2
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T49	2		T50	2		T65	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T49	3		T50	1		T65	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T49	1		T72	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T50	1		T123	1		T132	1