Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.90	96.97	55.32	84.72		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	134877921	22827	0	0
late_debug_enable_rd_A	134877921	4425	0	0
late_debug_enable_regwen_rd_A	134877921	4229	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134877921	22827	0	0
T46	144727	1505	0	0
T49	30745	3	0	0
T50	76534	3	0	0
T51	39516	40	0	0
T63	14147	28	0	0
T64	9052	4	0	0
T65	323333	2	0	0
T70	24943	789	0	0
T71	274159	39	0	0
T72	363983	2	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134877921	4425	0	0
T64	9052	14	0	0
T70	24943	183	0	0
T72	363983	76	0	0
T81	48919	24	0	0
T88	34983	74	0	0
T92	6052	8	0	0
T96	489816	220	0	0
T112	55307	33	0	0
T118	19623	93	0	0
T119	18083	132	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134877921	4229	0	0
T64	9052	19	0	0
T70	24943	163	0	0
T72	363983	94	0	0
T81	48919	5	0	0
T88	34983	96	0	0
T92	6052	2	0	0
T96	489816	263	0	0
T112	55307	42	0	0
T118	19623	38	0	0
T119	18083	122	0	0