Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9267134 |
9265934 |
0 |
0 |
selKnown1 |
76816856 |
76815656 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9267134 |
9265934 |
0 |
0 |
T1 |
91306 |
91302 |
0 |
0 |
T2 |
294 |
290 |
0 |
0 |
T3 |
60984 |
60980 |
0 |
0 |
T4 |
294 |
290 |
0 |
0 |
T9 |
3210 |
3206 |
0 |
0 |
T10 |
9131 |
9127 |
0 |
0 |
T14 |
0 |
12 |
0 |
0 |
T16 |
0 |
10 |
0 |
0 |
T17 |
0 |
2 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
218 |
214 |
0 |
0 |
T25 |
222 |
218 |
0 |
0 |
T26 |
218 |
214 |
0 |
0 |
T27 |
288 |
284 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T43 |
0 |
40 |
0 |
0 |
T53 |
0 |
22 |
0 |
0 |
T59 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
76816856 |
76815656 |
0 |
0 |
T1 |
187250 |
187246 |
0 |
0 |
T2 |
4435 |
4431 |
0 |
0 |
T3 |
221435 |
221431 |
0 |
0 |
T4 |
2890 |
2886 |
0 |
0 |
T6 |
0 |
10 |
0 |
0 |
T9 |
7479 |
7475 |
0 |
0 |
T10 |
14139 |
14135 |
0 |
0 |
T14 |
0 |
12 |
0 |
0 |
T16 |
0 |
10 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
3746 |
3742 |
0 |
0 |
T25 |
2233 |
2229 |
0 |
0 |
T26 |
2637 |
2633 |
0 |
0 |
T27 |
1801 |
1797 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T43 |
0 |
40 |
0 |
0 |
T53 |
0 |
22 |
0 |
0 |
T59 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
3065846 |
3065655 |
0 |
0 |
selKnown1 |
70615836 |
70615645 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3065846 |
3065655 |
0 |
0 |
T1 |
45638 |
45637 |
0 |
0 |
T2 |
146 |
145 |
0 |
0 |
T3 |
30489 |
30488 |
0 |
0 |
T4 |
146 |
145 |
0 |
0 |
T9 |
1604 |
1603 |
0 |
0 |
T10 |
4563 |
4562 |
0 |
0 |
T24 |
108 |
107 |
0 |
0 |
T25 |
110 |
109 |
0 |
0 |
T26 |
108 |
107 |
0 |
0 |
T27 |
143 |
142 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
70615836 |
70615645 |
0 |
0 |
T1 |
141602 |
141601 |
0 |
0 |
T2 |
4287 |
4286 |
0 |
0 |
T3 |
190940 |
190939 |
0 |
0 |
T4 |
2742 |
2741 |
0 |
0 |
T9 |
5873 |
5872 |
0 |
0 |
T10 |
9574 |
9573 |
0 |
0 |
T24 |
3636 |
3635 |
0 |
0 |
T25 |
2121 |
2120 |
0 |
0 |
T26 |
2527 |
2526 |
0 |
0 |
T27 |
1656 |
1655 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
487 |
296 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
3 |
2 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T53 |
0 |
11 |
0 |
0 |
T59 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
450 |
259 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
3 |
2 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T6 |
0 |
5 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T53 |
0 |
11 |
0 |
0 |
T59 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6198988 |
6198579 |
0 |
0 |
selKnown1 |
6198988 |
6198579 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6198988 |
6198579 |
0 |
0 |
T1 |
45638 |
45637 |
0 |
0 |
T2 |
146 |
145 |
0 |
0 |
T3 |
30489 |
30488 |
0 |
0 |
T4 |
146 |
145 |
0 |
0 |
T9 |
1604 |
1603 |
0 |
0 |
T10 |
4563 |
4562 |
0 |
0 |
T24 |
108 |
107 |
0 |
0 |
T25 |
110 |
109 |
0 |
0 |
T26 |
108 |
107 |
0 |
0 |
T27 |
143 |
142 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6198988 |
6198579 |
0 |
0 |
T1 |
45638 |
45637 |
0 |
0 |
T2 |
146 |
145 |
0 |
0 |
T3 |
30489 |
30488 |
0 |
0 |
T4 |
146 |
145 |
0 |
0 |
T9 |
1604 |
1603 |
0 |
0 |
T10 |
4563 |
4562 |
0 |
0 |
T24 |
108 |
107 |
0 |
0 |
T25 |
110 |
109 |
0 |
0 |
T26 |
108 |
107 |
0 |
0 |
T27 |
143 |
142 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1813 |
1404 |
0 |
0 |
selKnown1 |
1582 |
1173 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1813 |
1404 |
0 |
0 |
T1 |
25 |
24 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
3 |
2 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
4 |
3 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T53 |
0 |
11 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1582 |
1173 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
3 |
2 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T6 |
0 |
5 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T27 |
1 |
0 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T53 |
0 |
11 |
0 |
0 |
T59 |
0 |
2 |
0 |
0 |