Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_secded_inv_39_32_enc
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_regs.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen 100.00 100.00
tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen 100.00 100.00
tb.dut.tl_adapter_host_sba.u_cmd_intg_gen.gen_data_intg.u_data_gen 100.00 100.00
tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen 100.00 100.00
tb.dut.i_tlul_adapter_reg.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen 100.00 100.00


Module Instance : tb.dut.u_reg_regs.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.tl_adapter_host_sba.u_cmd_intg_gen.gen_data_intg.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_cmd_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i_tlul_adapter_reg.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_secded_inv_39_32_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.u_reg_regs.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.tl_adapter_host_sba.u_cmd_intg_gen.gen_data_intg.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.i_tlul_adapter_reg.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%