Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	243590	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	630798	1		T1	66		T3	24		T4	8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	551365	1		T1	40		T3	6		T5	16
values[0x0]	157121	1		T1	36		T3	32		T4	17
values[0x1]	165902	1		T1	39		T3	30		T4	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	183976	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	690412	1		T1	71		T3	28		T4	12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3271	1		T1	1		T46	1		T26	1
valid_sources[0x01]	3448	1		T3	10		T14	2		T133	1
valid_sources[0x02]	3903	1		T1	1		T14	2		T17	1
valid_sources[0x03]	2965	1		T5	5		T17	1		T33	2
valid_sources[0x04]	3602	1		T30	1		T133	1		T53	2
valid_sources[0x05]	3245	1		T14	1		T28	1		T35	1
valid_sources[0x06]	3226	1		T3	10		T5	3		T28	2
valid_sources[0x07]	3323	1		T1	1		T5	1		T29	20
valid_sources[0x08]	3233	1		T4	2		T5	1		T62	1
valid_sources[0x09]	3576	1		T46	2		T55	96		T44	4
valid_sources[0x0a]	3207	1		T1	1		T14	3		T33	4
valid_sources[0x0b]	4009	1		T17	1		T54	5		T53	3
valid_sources[0x0c]	3294	1		T1	1		T28	1		T55	114
valid_sources[0x0d]	3523	1		T27	80		T134	3		T135	1
valid_sources[0x0e]	3575	1		T1	1		T62	1		T26	1
valid_sources[0x0f]	5411	1		T134	1		T133	1		T53	1
valid_sources[0x10]	3444	1		T1	1		T4	4		T14	1
valid_sources[0x11]	3223	1		T1	1		T46	1		T26	1
valid_sources[0x12]	3366	1		T1	1		T14	4		T134	1
valid_sources[0x13]	3315	1		T5	1		T134	1		T17	1
valid_sources[0x14]	3660	1		T136	1		T133	1		T33	5
valid_sources[0x15]	3578	1		T3	1		T5	5		T14	2
valid_sources[0x16]	3067	1		T28	1		T133	3		T31	2
valid_sources[0x17]	3255	1		T17	2		T53	1		T55	106
valid_sources[0x18]	3359	1		T28	1		T46	1		T61	1
valid_sources[0x19]	3603	1		T1	6		T136	1		T133	3
valid_sources[0x1a]	3158	1		T46	3		T136	2		T35	5
valid_sources[0x1b]	3388	1		T14	3		T134	3		T55	99
valid_sources[0x1c]	3499	1		T26	1		T133	1		T137	1
valid_sources[0x1d]	3280	1		T28	2		T26	1		T133	2
valid_sources[0x1e]	3267	1		T14	2		T46	2		T54	8
valid_sources[0x1f]	3560	1		T26	1		T53	5		T55	113
valid_sources[0x20]	2974	1		T3	17		T4	1		T14	2
valid_sources[0x21]	3561	1		T5	1		T28	1		T138	50
valid_sources[0x22]	3394	1		T133	1		T33	7		T55	103
valid_sources[0x23]	3410	1		T1	1		T35	2		T55	107
valid_sources[0x24]	3238	1		T136	1		T35	1		T17	1
valid_sources[0x25]	3056	1		T3	2		T28	1		T61	1
valid_sources[0x26]	3689	1		T133	1		T17	1		T53	4
valid_sources[0x27]	3301	1		T5	2		T14	1		T28	2
valid_sources[0x28]	3699	1		T28	2		T139	40		T55	99
valid_sources[0x29]	4828	1		T4	2		T30	1		T33	1
valid_sources[0x2a]	3027	1		T1	2		T46	1		T26	1
valid_sources[0x2b]	3323	1		T46	1		T26	1		T36	6
valid_sources[0x2c]	3327	1		T133	1		T17	1		T54	4
valid_sources[0x2d]	3383	1		T14	1		T26	1		T133	3
valid_sources[0x2e]	3243	1		T1	1		T62	2		T136	1
valid_sources[0x2f]	3268	1		T5	5		T133	2		T17	1
valid_sources[0x30]	3181	1		T5	1		T134	4		T26	1
valid_sources[0x31]	3464	1		T1	4		T140	83		T53	2
valid_sources[0x32]	3301	1		T1	1		T4	1		T26	2
valid_sources[0x33]	3152	1		T54	20		T55	96		T44	1
valid_sources[0x34]	3462	1		T17	1		T54	19		T55	89
valid_sources[0x35]	3334	1		T1	1		T14	1		T46	1
valid_sources[0x36]	3464	1		T1	2		T10	1		T26	1
valid_sources[0x37]	3162	1		T28	4		T46	1		T133	3
valid_sources[0x38]	3422	1		T14	7		T26	1		T137	4
valid_sources[0x39]	3216	1		T133	2		T53	1		T55	109
valid_sources[0x3a]	3667	1		T1	2		T5	4		T14	1
valid_sources[0x3b]	3033	1		T35	1		T17	1		T53	1
valid_sources[0x3c]	3226	1		T28	2		T133	1		T53	3
valid_sources[0x3d]	3267	1		T137	13		T54	8		T53	13
valid_sources[0x3e]	3617	1		T55	88		T83	266		T52	2
valid_sources[0x3f]	3289	1		T46	1		T133	2		T53	8
valid_sources[0x40]	3245	1		T28	1		T26	1		T54	12
valid_sources[0x41]	3733	1		T55	112		T44	3		T83	306
valid_sources[0x42]	3416	1		T35	1		T54	10		T55	104
valid_sources[0x43]	3254	1		T1	1		T26	1		T53	4
valid_sources[0x44]	3155	1		T1	2		T4	2		T46	1
valid_sources[0x45]	3519	1		T53	4		T55	103		T44	1
valid_sources[0x46]	3583	1		T5	8		T46	1		T133	2
valid_sources[0x47]	3217	1		T1	1		T14	2		T26	1
valid_sources[0x48]	3200	1		T46	1		T35	1		T133	1
valid_sources[0x49]	3656	1		T1	2		T3	1		T14	3
valid_sources[0x4a]	3301	1		T26	1		T53	4		T55	107
valid_sources[0x4b]	3877	1		T14	1		T133	1		T138	2
valid_sources[0x4c]	3165	1		T17	1		T54	2		T55	111
valid_sources[0x4d]	3358	1		T28	1		T17	1		T33	1
valid_sources[0x4e]	3213	1		T1	1		T35	1		T141	1
valid_sources[0x4f]	3515	1		T4	1		T53	5		T55	97
valid_sources[0x50]	3136	1		T134	1		T26	1		T35	1
valid_sources[0x51]	3749	1		T136	1		T55	108		T44	3
valid_sources[0x52]	3234	1		T136	1		T26	1		T142	1
valid_sources[0x53]	3749	1		T1	3		T136	1		T133	3
valid_sources[0x54]	3339	1		T1	1		T137	11		T55	109
valid_sources[0x55]	3270	1		T5	1		T55	111		T44	5
valid_sources[0x56]	3471	1		T10	1		T14	1		T33	1
valid_sources[0x57]	3526	1		T143	40		T53	6		T55	112
valid_sources[0x58]	3289	1		T35	1		T133	1		T17	1
valid_sources[0x59]	2970	1		T134	2		T35	1		T133	3
valid_sources[0x5a]	3291	1		T133	1		T53	1		T55	116
valid_sources[0x5b]	3234	1		T1	4		T26	1		T33	6
valid_sources[0x5c]	3077	1		T35	2		T133	1		T54	14
valid_sources[0x5d]	3297	1		T4	2		T35	1		T53	4
valid_sources[0x5e]	3448	1		T4	1		T14	1		T26	1
valid_sources[0x5f]	3126	1		T4	1		T14	4		T33	1
valid_sources[0x60]	3363	1		T5	3		T28	2		T133	1
valid_sources[0x61]	3545	1		T1	1		T133	1		T53	11
valid_sources[0x62]	3512	1		T26	1		T135	1		T53	3
valid_sources[0x63]	3359	1		T1	1		T10	1		T35	2
valid_sources[0x64]	3375	1		T138	32		T53	2		T55	101
valid_sources[0x65]	3113	1		T26	1		T35	1		T53	8
valid_sources[0x66]	3951	1		T4	1		T134	5		T135	1
valid_sources[0x67]	4266	1		T4	4		T28	4		T46	1
valid_sources[0x68]	2890	1		T26	1		T33	1		T53	1
valid_sources[0x69]	3585	1		T133	1		T33	1		T53	1
valid_sources[0x6a]	3352	1		T1	2		T14	2		T62	1
valid_sources[0x6b]	3436	1		T1	1		T46	2		T134	1
valid_sources[0x6c]	3609	1		T5	1		T133	1		T17	1
valid_sources[0x6d]	3706	1		T14	1		T136	1		T55	107
valid_sources[0x6e]	3754	1		T53	2		T55	85		T44	2
valid_sources[0x6f]	3687	1		T54	3		T55	119		T44	4
valid_sources[0x70]	3359	1		T5	19		T26	1		T33	1
valid_sources[0x71]	3398	1		T53	4		T55	117		T44	1
valid_sources[0x72]	3746	1		T133	1		T55	114		T44	3
valid_sources[0x73]	3591	1		T30	2		T54	8		T53	1
valid_sources[0x74]	4114	1		T1	1		T134	1		T26	1
valid_sources[0x75]	3700	1		T3	10		T136	2		T134	1
valid_sources[0x76]	3379	1		T54	6		T53	1		T55	101
valid_sources[0x77]	3359	1		T14	5		T28	1		T26	1
valid_sources[0x78]	3251	1		T28	2		T26	1		T55	97
valid_sources[0x79]	3866	1		T28	3		T135	1		T17	1
valid_sources[0x7a]	3355	1		T1	2		T30	2		T17	1
valid_sources[0x7b]	3366	1		T1	1		T53	1		T55	98
valid_sources[0x7c]	3787	1		T1	1		T14	2		T33	1
valid_sources[0x7d]	3267	1		T1	1		T35	1		T133	1
valid_sources[0x7e]	3216	1		T3	4		T28	1		T144	1
valid_sources[0x7f]	3037	1		T1	1		T28	4		T145	2
valid_sources[0x80]	3477	1		T4	1		T10	1		T35	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

322180

1

T1

20

T3

5

T5

8

values[0x0]

all_enables

biggest_size

154397

1

T1

25

T3

14

T4

3

values[0x1]

all_enables

biggest_size

154221

1

T1

21

T3

5

T4

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5623	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	28232	1		T20	1		T21	4		T22	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12429	1		T54	3		T53	3		T55	284
values[0x0]	10485	1		T19	1		T20	3		T21	6
values[0x1]	10941	1		T19	2		T20	2		T21	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4293	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	29562	1		T20	2		T21	5		T22	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	155	1		T55	1		T44	5		T83	2
valid_sources[0x01]	95	1		T74	1		T77	2		T146	1
valid_sources[0x02]	133	1		T146	1		T55	1		T44	6
valid_sources[0x03]	121	1		T44	2		T83	6		T52	2
valid_sources[0x04]	125	1		T44	3		T83	1		T50	1
valid_sources[0x05]	111	1		T21	2		T75	2		T147	2
valid_sources[0x06]	129	1		T82	13		T148	1		T55	1
valid_sources[0x07]	113	1		T55	3		T44	6		T83	3
valid_sources[0x08]	115	1		T146	4		T149	1		T150	1
valid_sources[0x09]	93	1		T151	1		T152	1		T153	1
valid_sources[0x0a]	141	1		T73	9		T76	1		T55	1
valid_sources[0x0b]	127	1		T153	1		T44	3		T52	1
valid_sources[0x0c]	99	1		T44	4		T83	4		T52	1
valid_sources[0x0d]	84	1		T74	1		T44	4		T83	4
valid_sources[0x0e]	125	1		T119	1		T154	1		T55	6
valid_sources[0x0f]	79	1		T20	1		T74	1		T63	1
valid_sources[0x10]	285	1		T154	5		T153	1		T55	2
valid_sources[0x11]	131	1		T155	1		T44	4		T83	4
valid_sources[0x12]	120	1		T55	1		T44	5		T83	4
valid_sources[0x13]	152	1		T73	1		T152	1		T44	10
valid_sources[0x14]	122	1		T155	1		T44	6		T83	7
valid_sources[0x15]	107	1		T156	1		T157	1		T55	3
valid_sources[0x16]	321	1		T21	1		T152	1		T55	1
valid_sources[0x17]	76	1		T44	1		T83	3		T52	1
valid_sources[0x18]	117	1		T158	1		T44	6		T83	3
valid_sources[0x19]	119	1		T44	7		T83	3		T52	1
valid_sources[0x1a]	145	1		T44	5		T83	2		T45	5
valid_sources[0x1b]	91	1		T44	3		T83	3		T52	1
valid_sources[0x1c]	94	1		T73	1		T75	2		T63	1
valid_sources[0x1d]	198	1		T75	1		T76	1		T155	1
valid_sources[0x1e]	115	1		T63	2		T149	1		T44	2
valid_sources[0x1f]	113	1		T153	2		T44	1		T83	2
valid_sources[0x20]	119	1		T159	2		T44	1		T83	2
valid_sources[0x21]	85	1		T44	1		T83	2		T52	1
valid_sources[0x22]	147	1		T159	1		T160	5		T44	5
valid_sources[0x23]	197	1		T158	3		T151	1		T44	3
valid_sources[0x24]	182	1		T152	1		T55	2		T44	3
valid_sources[0x25]	202	1		T161	1		T153	1		T54	1
valid_sources[0x26]	109	1		T44	2		T83	2		T45	3
valid_sources[0x27]	68	1		T44	2		T83	2		T52	1
valid_sources[0x28]	78	1		T83	4		T45	7		T66	7
valid_sources[0x29]	838	1		T44	7		T83	4		T45	3
valid_sources[0x2a]	95	1		T159	2		T55	3		T44	9
valid_sources[0x2b]	151	1		T162	6		T55	3		T44	2
valid_sources[0x2c]	58	1		T55	1		T45	2		T66	8
valid_sources[0x2d]	84	1		T82	1		T55	6		T44	4
valid_sources[0x2e]	93	1		T160	2		T55	5		T44	1
valid_sources[0x2f]	243	1		T163	1		T55	4		T44	3
valid_sources[0x30]	70	1		T44	3		T83	3		T45	5
valid_sources[0x31]	92	1		T44	6		T83	5		T52	1
valid_sources[0x32]	84	1		T21	1		T63	3		T151	1
valid_sources[0x33]	86	1		T21	1		T44	4		T83	6
valid_sources[0x34]	123	1		T44	1		T83	2		T71	5
valid_sources[0x35]	90	1		T44	1		T83	2		T52	4
valid_sources[0x36]	123	1		T73	1		T44	5		T83	9
valid_sources[0x37]	97	1		T164	2		T150	1		T44	4
valid_sources[0x38]	108	1		T44	1		T83	5		T50	2
valid_sources[0x39]	75	1		T119	1		T165	1		T44	3
valid_sources[0x3a]	122	1		T21	2		T115	2		T44	2
valid_sources[0x3b]	99	1		T150	1		T44	2		T83	2
valid_sources[0x3c]	96	1		T151	2		T44	5		T83	4
valid_sources[0x3d]	92	1		T146	3		T44	6		T83	6
valid_sources[0x3e]	93	1		T55	5		T44	1		T83	4
valid_sources[0x3f]	94	1		T44	2		T83	6		T52	1
valid_sources[0x40]	199	1		T149	1		T153	1		T55	3
valid_sources[0x41]	140	1		T44	1		T83	6		T45	2
valid_sources[0x42]	129	1		T20	2		T21	1		T157	1
valid_sources[0x43]	78	1		T54	2		T44	5		T83	4
valid_sources[0x44]	95	1		T166	1		T55	1		T44	8
valid_sources[0x45]	108	1		T44	6		T83	2		T45	3
valid_sources[0x46]	88	1		T165	2		T44	6		T83	1
valid_sources[0x47]	102	1		T21	1		T74	1		T44	6
valid_sources[0x48]	108	1		T167	1		T44	3		T83	3
valid_sources[0x49]	109	1		T83	2		T50	1		T45	3
valid_sources[0x4a]	142	1		T164	1		T44	2		T83	2
valid_sources[0x4b]	107	1		T44	1		T83	5		T52	2
valid_sources[0x4c]	121	1		T49	1		T44	2		T83	3
valid_sources[0x4d]	82	1		T157	1		T44	4		T83	1
valid_sources[0x4e]	107	1		T44	7		T83	4		T71	1
valid_sources[0x4f]	114	1		T22	9		T55	4		T83	4
valid_sources[0x50]	81	1		T19	3		T44	3		T83	1
valid_sources[0x51]	169	1		T148	1		T55	10		T44	3
valid_sources[0x52]	101	1		T74	1		T82	3		T153	1
valid_sources[0x53]	229	1		T55	1		T44	1		T83	2
valid_sources[0x54]	103	1		T166	1		T44	3		T83	1
valid_sources[0x55]	88	1		T54	2		T44	2		T83	2
valid_sources[0x56]	129	1		T49	1		T146	1		T147	2
valid_sources[0x57]	98	1		T152	3		T44	5		T52	1
valid_sources[0x58]	97	1		T150	1		T44	2		T83	4
valid_sources[0x59]	432	1		T149	1		T44	6		T83	5
valid_sources[0x5a]	86	1		T55	5		T44	1		T83	1
valid_sources[0x5b]	181	1		T165	1		T168	1		T44	1
valid_sources[0x5c]	123	1		T44	7		T83	3		T52	1
valid_sources[0x5d]	202	1		T49	1		T155	1		T55	2
valid_sources[0x5e]	103	1		T44	5		T83	3		T51	2
valid_sources[0x5f]	70	1		T153	1		T55	5		T44	5
valid_sources[0x60]	88	1		T44	3		T83	1		T52	3
valid_sources[0x61]	241	1		T146	1		T147	4		T157	1
valid_sources[0x62]	140	1		T155	2		T55	1		T44	1
valid_sources[0x63]	190	1		T75	2		T55	1		T83	1
valid_sources[0x64]	141	1		T77	1		T157	1		T55	1
valid_sources[0x65]	307	1		T55	6		T44	4		T83	4
valid_sources[0x66]	110	1		T158	1		T44	5		T83	2
valid_sources[0x67]	135	1		T75	1		T55	2		T44	4
valid_sources[0x68]	138	1		T55	2		T44	5		T83	2
valid_sources[0x69]	100	1		T166	1		T158	2		T55	2
valid_sources[0x6a]	80	1		T158	1		T55	3		T44	2
valid_sources[0x6b]	112	1		T21	1		T169	2		T55	3
valid_sources[0x6c]	87	1		T44	5		T83	6		T52	4
valid_sources[0x6d]	83	1		T73	1		T159	3		T44	4
valid_sources[0x6e]	79	1		T44	3		T83	1		T50	2
valid_sources[0x6f]	119	1		T55	1		T44	4		T83	7
valid_sources[0x70]	100	1		T49	2		T44	1		T83	5
valid_sources[0x71]	56	1		T44	6		T83	2		T52	1
valid_sources[0x72]	96	1		T55	1		T44	3		T83	3
valid_sources[0x73]	142	1		T153	1		T55	4		T44	2
valid_sources[0x74]	82	1		T77	2		T159	1		T44	2
valid_sources[0x75]	88	1		T119	1		T44	1		T83	2
valid_sources[0x76]	75	1		T73	2		T44	6		T83	1
valid_sources[0x77]	157	1		T77	3		T164	4		T161	1
valid_sources[0x78]	182	1		T147	2		T151	1		T55	8
valid_sources[0x79]	123	1		T44	1		T83	4		T52	1
valid_sources[0x7a]	167	1		T44	3		T83	2		T52	2
valid_sources[0x7b]	170	1		T170	1		T44	2		T83	2
valid_sources[0x7c]	103	1		T158	2		T44	6		T83	1
valid_sources[0x7d]	89	1		T20	2		T21	1		T163	4
valid_sources[0x7e]	114	1		T149	2		T55	2		T44	5
valid_sources[0x7f]	106	1		T75	1		T119	1		T44	4
valid_sources[0x80]	210	1		T171	13		T172	1		T153	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9069

1

T54

2

T53

1

T55

147

values[0x0]

all_enables

biggest_size

9643

1

T20

1

T21

1

T22

2

values[0x1]

all_enables

biggest_size

9520

1

T21

3

T73

1

T82

1