Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
312993 |
1 |
|
T1 |
49 |
|
T3 |
44 |
|
T4 |
32 |
full_word |
633328 |
1 |
|
T1 |
66 |
|
T3 |
24 |
|
T4 |
8 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
946031 |
1 |
|
T1 |
115 |
|
T3 |
68 |
|
T4 |
40 |
auto[TlIntgErrCmd] |
84 |
1 |
|
T50 |
5 |
|
T90 |
7 |
|
T80 |
3 |
auto[TlIntgErrData] |
110 |
1 |
|
T50 |
1 |
|
T90 |
7 |
|
T80 |
4 |
auto[TlIntgErrBoth] |
96 |
1 |
|
T50 |
14 |
|
T90 |
6 |
|
T80 |
3 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
554353 |
1 |
|
T1 |
40 |
|
T3 |
6 |
|
T5 |
16 |
auto[1] |
391968 |
1 |
|
T1 |
75 |
|
T3 |
62 |
|
T4 |
40 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
1 |
15 |
93.75 |
1 |
Automatically Generated Cross Bins for cr_all
Uncovered bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | NUMBER |
[auto[TlIntgErrCmd]] |
[full_word] |
[auto[1]] |
0 |
1 |
1 |
Covered bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
231720 |
1 |
|
T1 |
20 |
|
T3 |
1 |
|
T5 |
8 |
auto[TlIntgErrNone] |
partial |
auto[1] |
81009 |
1 |
|
T1 |
29 |
|
T3 |
43 |
|
T4 |
32 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
322496 |
1 |
|
T1 |
20 |
|
T3 |
5 |
|
T5 |
8 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
310806 |
1 |
|
T1 |
46 |
|
T3 |
19 |
|
T4 |
8 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
32 |
1 |
|
T50 |
2 |
|
T90 |
4 |
|
T80 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
47 |
1 |
|
T50 |
3 |
|
T90 |
3 |
|
T80 |
2 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
5 |
1 |
|
T123 |
1 |
|
T124 |
2 |
|
T125 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
53 |
1 |
|
T50 |
1 |
|
T90 |
3 |
|
T80 |
2 |
auto[TlIntgErrData] |
partial |
auto[1] |
48 |
1 |
|
T90 |
3 |
|
T80 |
2 |
|
T123 |
3 |
auto[TlIntgErrData] |
full_word |
auto[0] |
4 |
1 |
|
T90 |
1 |
|
T126 |
1 |
|
T127 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
5 |
1 |
|
T125 |
1 |
|
T128 |
1 |
|
T129 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
38 |
1 |
|
T90 |
3 |
|
T80 |
1 |
|
T123 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
46 |
1 |
|
T50 |
9 |
|
T90 |
3 |
|
T80 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
5 |
1 |
|
T50 |
2 |
|
T125 |
1 |
|
T130 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
7 |
1 |
|
T50 |
3 |
|
T131 |
1 |
|
T132 |
2 |