Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 10821029 10819801 0 0
selKnown1 90979510 90978282 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 10821029 10819801 0 0
T1 85458 85454 0 0
T2 26054 26050 0 0
T3 84890 84886 0 0
T4 58656 58652 0 0
T5 0 41 0 0
T6 482 478 0 0
T8 21588 21584 0 0
T11 0 12 0 0
T12 0 2 0 0
T13 0 2 0 0
T14 0 23 0 0
T19 218 214 0 0
T20 218 214 0 0
T21 222 218 0 0
T22 298 294 0 0
T29 0 34 0 0
T46 0 24 0 0
T47 0 3 0 0
T48 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 90979510 90978282 0 0
T1 603158 603154 0 0
T2 453951 453947 0 0
T3 164515 164512 0 0
T4 841481 841477 0 0
T5 0 6 0 0
T6 5900 5896 0 0
T8 416403 416399 0 0
T11 0 12 0 0
T12 0 2 0 0
T13 0 2 0 0
T14 0 8 0 0
T19 3842 3838 0 0
T20 2519 2515 0 0
T21 12358 12354 0 0
T22 4775 4771 0 0
T29 0 10 0 0
T46 0 10 0 0
T48 0 12 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 3195646 3195448 0 0
selKnown1 83354545 83354347 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 3195646 3195448 0 0
T1 42722 42721 0 0
T2 13026 13025 0 0
T3 42439 42438 0 0
T4 29327 29326 0 0
T6 240 239 0 0
T8 10793 10792 0 0
T19 108 107 0 0
T20 108 107 0 0
T21 110 109 0 0
T22 148 147 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 83354545 83354347 0 0
T1 560422 560421 0 0
T2 440923 440922 0 0
T3 122066 122066 0 0
T4 812152 812151 0 0
T6 5658 5657 0 0
T8 405608 405607 0 0
T19 3732 3731 0 0
T20 2409 2408 0 0
T21 12246 12245 0 0
T22 4625 4624 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 586 388 0 0
selKnown1 477 279 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 586 388 0 0
T1 7 6 0 0
T2 1 0 0 0
T3 5 4 0 0
T4 1 0 0 0
T5 0 16 0 0
T6 1 0 0 0
T8 1 0 0 0
T11 0 6 0 0
T12 0 1 0 0
T13 0 1 0 0
T14 0 4 0 0
T19 1 0 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 1 0 0 0
T29 0 17 0 0
T46 0 12 0 0
T48 0 6 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 477 279 0 0
T1 7 6 0 0
T2 1 0 0 0
T3 5 4 0 0
T4 1 0 0 0
T5 0 3 0 0
T6 1 0 0 0
T8 1 0 0 0
T11 0 6 0 0
T12 0 1 0 0
T13 0 1 0 0
T14 0 4 0 0
T19 1 0 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 1 0 0 0
T29 0 5 0 0
T46 0 5 0 0
T48 0 6 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 7622886 7622470 0 0
selKnown1 7622886 7622470 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 7622886 7622470 0 0
T1 42722 42721 0 0
T2 13026 13025 0 0
T3 42439 42438 0 0
T4 29327 29326 0 0
T6 240 239 0 0
T8 10793 10792 0 0
T19 108 107 0 0
T20 108 107 0 0
T21 110 109 0 0
T22 148 147 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 7622886 7622470 0 0
T1 42722 42721 0 0
T2 13026 13025 0 0
T3 42439 42438 0 0
T4 29327 29326 0 0
T6 240 239 0 0
T8 10793 10792 0 0
T19 108 107 0 0
T20 108 107 0 0
T21 110 109 0 0
T22 148 147 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1911 1495 0 0
selKnown1 1602 1186 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1911 1495 0 0
T1 7 6 0 0
T2 1 0 0 0
T3 7 6 0 0
T4 1 0 0 0
T5 0 25 0 0
T6 1 0 0 0
T8 1 0 0 0
T11 0 6 0 0
T12 0 1 0 0
T13 0 1 0 0
T14 0 19 0 0
T19 1 0 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 1 0 0 0
T29 0 17 0 0
T46 0 12 0 0
T47 0 3 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1602 1186 0 0
T1 7 6 0 0
T2 1 0 0 0
T3 5 4 0 0
T4 1 0 0 0
T5 0 3 0 0
T6 1 0 0 0
T8 1 0 0 0
T11 0 6 0 0
T12 0 1 0 0
T13 0 1 0 0
T14 0 4 0 0
T19 1 0 0 0
T20 1 0 0 0
T21 1 0 0 0
T22 1 0 0 0
T29 0 5 0 0
T46 0 5 0 0
T48 0 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%