SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.85 | 96.97 | 55.32 | 89.47 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.85 | 96.97 | 55.32 | 89.47 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.85 | 96.97 | 55.32 | 89.47 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.85 | 96.97 | 55.32 | 89.47 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
58.07 | 78.43 | 66.67 | 28.57 | 66.67 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.58 | 96.08 | 77.78 | 85.71 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1188 | 1188 | 0 | 0 |
OutputsKnown_A | 500127270 | 499938240 | 0 | 0 |
gen_flops.OutputDelay_A | 250063635 | 249964827 | 0 | 1782 |
gen_no_flops.OutputDelay_A | 250063635 | 249969120 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1188 | 1188 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T19 | 6 | 6 | 0 | 0 |
T20 | 6 | 6 | 0 | 0 |
T21 | 6 | 6 | 0 | 0 |
T22 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 500127270 | 499938240 | 0 | 0 |
T1 | 3362532 | 3359880 | 0 | 0 |
T2 | 2645538 | 2645142 | 0 | 0 |
T3 | 732396 | 732204 | 0 | 0 |
T4 | 4872912 | 4872342 | 0 | 0 |
T6 | 33948 | 33546 | 0 | 0 |
T8 | 2433648 | 2433330 | 0 | 0 |
T19 | 22392 | 22080 | 0 | 0 |
T20 | 14454 | 14064 | 0 | 0 |
T21 | 73476 | 73080 | 0 | 0 |
T22 | 27750 | 27432 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 250063635 | 249964827 | 0 | 1782 |
T1 | 1681266 | 1679877 | 0 | 9 |
T2 | 1322769 | 1322562 | 0 | 9 |
T3 | 366198 | 366099 | 0 | 9 |
T4 | 2436456 | 2436162 | 0 | 9 |
T6 | 16974 | 16764 | 0 | 9 |
T8 | 1216824 | 1216656 | 0 | 9 |
T19 | 11196 | 11031 | 0 | 9 |
T20 | 7227 | 7023 | 0 | 9 |
T21 | 36738 | 36531 | 0 | 9 |
T22 | 13875 | 13707 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 250063635 | 249969120 | 0 | 0 |
T1 | 1681266 | 1679940 | 0 | 0 |
T2 | 1322769 | 1322571 | 0 | 0 |
T3 | 366198 | 366102 | 0 | 0 |
T4 | 2436456 | 2436171 | 0 | 0 |
T6 | 16974 | 16773 | 0 | 0 |
T8 | 1216824 | 1216665 | 0 | 0 |
T19 | 11196 | 11040 | 0 | 0 |
T20 | 7227 | 7032 | 0 | 0 |
T21 | 36738 | 36540 | 0 | 0 |
T22 | 13875 | 13716 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 198 | 198 | 0 | 0 |
OutputsKnown_A | 83354545 | 83323040 | 0 | 0 |
gen_flops.OutputDelay_A | 83354545 | 83321609 | 0 | 594 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 198 | 198 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83323040 | 0 | 0 |
T1 | 560422 | 559980 | 0 | 0 |
T2 | 440923 | 440857 | 0 | 0 |
T3 | 122066 | 122034 | 0 | 0 |
T4 | 812152 | 812057 | 0 | 0 |
T6 | 5658 | 5591 | 0 | 0 |
T8 | 405608 | 405555 | 0 | 0 |
T19 | 3732 | 3680 | 0 | 0 |
T20 | 2409 | 2344 | 0 | 0 |
T21 | 12246 | 12180 | 0 | 0 |
T22 | 4625 | 4572 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83321609 | 0 | 594 |
T1 | 560422 | 559959 | 0 | 3 |
T2 | 440923 | 440854 | 0 | 3 |
T3 | 122066 | 122033 | 0 | 3 |
T4 | 812152 | 812054 | 0 | 3 |
T6 | 5658 | 5588 | 0 | 3 |
T8 | 405608 | 405552 | 0 | 3 |
T19 | 3732 | 3677 | 0 | 3 |
T20 | 2409 | 2341 | 0 | 3 |
T21 | 12246 | 12177 | 0 | 3 |
T22 | 4625 | 4569 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 198 | 198 | 0 | 0 |
OutputsKnown_A | 83354545 | 83323040 | 0 | 0 |
gen_flops.OutputDelay_A | 83354545 | 83321609 | 0 | 594 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 198 | 198 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83323040 | 0 | 0 |
T1 | 560422 | 559980 | 0 | 0 |
T2 | 440923 | 440857 | 0 | 0 |
T3 | 122066 | 122034 | 0 | 0 |
T4 | 812152 | 812057 | 0 | 0 |
T6 | 5658 | 5591 | 0 | 0 |
T8 | 405608 | 405555 | 0 | 0 |
T19 | 3732 | 3680 | 0 | 0 |
T20 | 2409 | 2344 | 0 | 0 |
T21 | 12246 | 12180 | 0 | 0 |
T22 | 4625 | 4572 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83321609 | 0 | 594 |
T1 | 560422 | 559959 | 0 | 3 |
T2 | 440923 | 440854 | 0 | 3 |
T3 | 122066 | 122033 | 0 | 3 |
T4 | 812152 | 812054 | 0 | 3 |
T6 | 5658 | 5588 | 0 | 3 |
T8 | 405608 | 405552 | 0 | 3 |
T19 | 3732 | 3677 | 0 | 3 |
T20 | 2409 | 2341 | 0 | 3 |
T21 | 12246 | 12177 | 0 | 3 |
T22 | 4625 | 4569 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 198 | 198 | 0 | 0 |
OutputsKnown_A | 83354545 | 83323040 | 0 | 0 |
gen_no_flops.OutputDelay_A | 83354545 | 83323040 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 198 | 198 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83323040 | 0 | 0 |
T1 | 560422 | 559980 | 0 | 0 |
T2 | 440923 | 440857 | 0 | 0 |
T3 | 122066 | 122034 | 0 | 0 |
T4 | 812152 | 812057 | 0 | 0 |
T6 | 5658 | 5591 | 0 | 0 |
T8 | 405608 | 405555 | 0 | 0 |
T19 | 3732 | 3680 | 0 | 0 |
T20 | 2409 | 2344 | 0 | 0 |
T21 | 12246 | 12180 | 0 | 0 |
T22 | 4625 | 4572 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83323040 | 0 | 0 |
T1 | 560422 | 559980 | 0 | 0 |
T2 | 440923 | 440857 | 0 | 0 |
T3 | 122066 | 122034 | 0 | 0 |
T4 | 812152 | 812057 | 0 | 0 |
T6 | 5658 | 5591 | 0 | 0 |
T8 | 405608 | 405555 | 0 | 0 |
T19 | 3732 | 3680 | 0 | 0 |
T20 | 2409 | 2344 | 0 | 0 |
T21 | 12246 | 12180 | 0 | 0 |
T22 | 4625 | 4572 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 198 | 198 | 0 | 0 |
OutputsKnown_A | 83354545 | 83323040 | 0 | 0 |
gen_flops.OutputDelay_A | 83354545 | 83321609 | 0 | 594 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 198 | 198 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83323040 | 0 | 0 |
T1 | 560422 | 559980 | 0 | 0 |
T2 | 440923 | 440857 | 0 | 0 |
T3 | 122066 | 122034 | 0 | 0 |
T4 | 812152 | 812057 | 0 | 0 |
T6 | 5658 | 5591 | 0 | 0 |
T8 | 405608 | 405555 | 0 | 0 |
T19 | 3732 | 3680 | 0 | 0 |
T20 | 2409 | 2344 | 0 | 0 |
T21 | 12246 | 12180 | 0 | 0 |
T22 | 4625 | 4572 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83321609 | 0 | 594 |
T1 | 560422 | 559959 | 0 | 3 |
T2 | 440923 | 440854 | 0 | 3 |
T3 | 122066 | 122033 | 0 | 3 |
T4 | 812152 | 812054 | 0 | 3 |
T6 | 5658 | 5588 | 0 | 3 |
T8 | 405608 | 405552 | 0 | 3 |
T19 | 3732 | 3677 | 0 | 3 |
T20 | 2409 | 2341 | 0 | 3 |
T21 | 12246 | 12177 | 0 | 3 |
T22 | 4625 | 4569 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 198 | 198 | 0 | 0 |
OutputsKnown_A | 83354545 | 83323040 | 0 | 0 |
gen_no_flops.OutputDelay_A | 83354545 | 83323040 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 198 | 198 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83323040 | 0 | 0 |
T1 | 560422 | 559980 | 0 | 0 |
T2 | 440923 | 440857 | 0 | 0 |
T3 | 122066 | 122034 | 0 | 0 |
T4 | 812152 | 812057 | 0 | 0 |
T6 | 5658 | 5591 | 0 | 0 |
T8 | 405608 | 405555 | 0 | 0 |
T19 | 3732 | 3680 | 0 | 0 |
T20 | 2409 | 2344 | 0 | 0 |
T21 | 12246 | 12180 | 0 | 0 |
T22 | 4625 | 4572 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83323040 | 0 | 0 |
T1 | 560422 | 559980 | 0 | 0 |
T2 | 440923 | 440857 | 0 | 0 |
T3 | 122066 | 122034 | 0 | 0 |
T4 | 812152 | 812057 | 0 | 0 |
T6 | 5658 | 5591 | 0 | 0 |
T8 | 405608 | 405555 | 0 | 0 |
T19 | 3732 | 3680 | 0 | 0 |
T20 | 2409 | 2344 | 0 | 0 |
T21 | 12246 | 12180 | 0 | 0 |
T22 | 4625 | 4572 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 198 | 198 | 0 | 0 |
OutputsKnown_A | 83354545 | 83323040 | 0 | 0 |
gen_no_flops.OutputDelay_A | 83354545 | 83323040 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 198 | 198 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83323040 | 0 | 0 |
T1 | 560422 | 559980 | 0 | 0 |
T2 | 440923 | 440857 | 0 | 0 |
T3 | 122066 | 122034 | 0 | 0 |
T4 | 812152 | 812057 | 0 | 0 |
T6 | 5658 | 5591 | 0 | 0 |
T8 | 405608 | 405555 | 0 | 0 |
T19 | 3732 | 3680 | 0 | 0 |
T20 | 2409 | 2344 | 0 | 0 |
T21 | 12246 | 12180 | 0 | 0 |
T22 | 4625 | 4572 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 83354545 | 83323040 | 0 | 0 |
T1 | 560422 | 559980 | 0 | 0 |
T2 | 440923 | 440857 | 0 | 0 |
T3 | 122066 | 122034 | 0 | 0 |
T4 | 812152 | 812057 | 0 | 0 |
T6 | 5658 | 5591 | 0 | 0 |
T8 | 405608 | 405555 | 0 | 0 |
T19 | 3732 | 3680 | 0 | 0 |
T20 | 2409 | 2344 | 0 | 0 |
T21 | 12246 | 12180 | 0 | 0 |
T22 | 4625 | 4572 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |