Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 185959 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 539594 1 T3 8 T7 5 T4 6



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 440812 1 T4 6 T6 6 T8 12
values[0x0] 138926 1 T3 15 T7 7 T4 4
values[0x1] 145815 1 T3 9 T7 5 T4 4



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 141925 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 583628 1 T3 8 T7 7 T4 7



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 2477 1 T136 1 T30 1 T51 2
valid_sources[0x01] 2883 1 T137 1 T31 2 T51 5
valid_sources[0x02] 2375 1 T8 1 T19 1 T34 4
valid_sources[0x03] 2658 1 T19 1 T26 2 T11 2
valid_sources[0x04] 2855 1 T26 1 T11 1 T137 1
valid_sources[0x05] 2746 1 T19 1 T138 2 T51 3
valid_sources[0x06] 2642 1 T8 3 T34 1 T139 1
valid_sources[0x07] 3306 1 T19 2 T11 2 T30 1
valid_sources[0x08] 2995 1 T31 1 T139 5 T51 1
valid_sources[0x09] 2924 1 T36 1 T51 1 T52 1
valid_sources[0x0a] 3058 1 T19 1 T37 1 T139 1
valid_sources[0x0b] 2731 1 T137 1 T51 3 T52 3
valid_sources[0x0c] 2511 1 T11 1 T139 1 T30 1
valid_sources[0x0d] 3243 1 T11 1 T140 3 T51 1
valid_sources[0x0e] 2460 1 T7 1 T32 1 T51 1
valid_sources[0x0f] 2848 1 T32 1 T140 1 T138 1
valid_sources[0x10] 3103 1 T139 1 T30 1 T51 2
valid_sources[0x11] 2934 1 T139 2 T51 2 T53 24
valid_sources[0x12] 2593 1 T10 4 T137 1 T51 5
valid_sources[0x13] 3028 1 T8 9 T137 3 T139 4
valid_sources[0x14] 3462 1 T7 2 T32 1 T51 2
valid_sources[0x15] 2982 1 T29 3 T26 1 T32 1
valid_sources[0x16] 2911 1 T19 1 T34 1 T32 1
valid_sources[0x17] 2734 1 T19 1 T32 2 T30 1
valid_sources[0x18] 2964 1 T19 2 T26 3 T30 1
valid_sources[0x19] 3077 1 T8 6 T138 1 T51 8
valid_sources[0x1a] 2354 1 T11 2 T140 4 T51 4
valid_sources[0x1b] 2980 1 T31 1 T139 1 T51 2
valid_sources[0x1c] 2681 1 T7 1 T19 1 T37 1
valid_sources[0x1d] 2953 1 T19 1 T26 1 T11 1
valid_sources[0x1e] 2524 1 T19 1 T32 1 T51 1
valid_sources[0x1f] 2885 1 T140 2 T51 7 T53 16
valid_sources[0x20] 2798 1 T138 1 T51 3 T52 4
valid_sources[0x21] 2342 1 T55 1 T19 1 T137 1
valid_sources[0x22] 2919 1 T34 2 T52 6 T53 43
valid_sources[0x23] 2671 1 T26 1 T51 2 T52 4
valid_sources[0x24] 2886 1 T8 2 T51 3 T52 21
valid_sources[0x25] 2812 1 T3 24 T11 1 T137 1
valid_sources[0x26] 3171 1 T19 1 T34 1 T33 1
valid_sources[0x27] 2911 1 T137 1 T51 7 T53 5
valid_sources[0x28] 2871 1 T37 2 T51 3 T52 9
valid_sources[0x29] 3111 1 T8 3 T13 1 T26 1
valid_sources[0x2a] 2798 1 T26 1 T139 3 T51 2
valid_sources[0x2b] 3141 1 T7 1 T8 2 T37 2
valid_sources[0x2c] 3739 1 T136 2 T28 80 T51 6
valid_sources[0x2d] 2791 1 T15 3 T10 10 T26 3
valid_sources[0x2e] 2831 1 T11 2 T137 1 T30 1
valid_sources[0x2f] 2942 1 T26 1 T32 1 T51 1
valid_sources[0x30] 2571 1 T37 1 T137 3 T31 6
valid_sources[0x31] 2829 1 T19 1 T51 2 T52 4
valid_sources[0x32] 2983 1 T19 1 T26 1 T11 1
valid_sources[0x33] 2903 1 T137 1 T35 1 T34 1
valid_sources[0x34] 2682 1 T55 1 T11 2 T51 1
valid_sources[0x35] 2977 1 T19 2 T137 1 T51 4
valid_sources[0x36] 2914 1 T29 2 T34 2 T139 3
valid_sources[0x37] 2627 1 T8 1 T137 2 T138 1
valid_sources[0x38] 3591 1 T26 3 T138 1 T51 3
valid_sources[0x39] 2862 1 T6 14 T34 1 T51 4
valid_sources[0x3a] 2557 1 T4 14 T8 1 T30 1
valid_sources[0x3b] 2445 1 T8 9 T55 1 T51 1
valid_sources[0x3c] 2935 1 T10 1 T51 3 T53 13
valid_sources[0x3d] 3040 1 T141 1 T32 1 T138 2
valid_sources[0x3e] 2735 1 T8 5 T26 2 T137 1
valid_sources[0x3f] 2961 1 T30 1 T52 1 T43 1
valid_sources[0x40] 2668 1 T26 3 T137 1 T31 1
valid_sources[0x41] 3036 1 T31 1 T142 1 T52 10
valid_sources[0x42] 2513 1 T55 1 T11 1 T137 1
valid_sources[0x43] 2721 1 T7 1 T19 2 T26 3
valid_sources[0x44] 2790 1 T51 1 T52 1 T53 72
valid_sources[0x45] 2485 1 T19 1 T141 1 T51 6
valid_sources[0x46] 2844 1 T11 1 T137 1 T32 2
valid_sources[0x47] 2674 1 T8 2 T19 1 T11 4
valid_sources[0x48] 2407 1 T19 1 T34 2 T31 1
valid_sources[0x49] 2815 1 T19 1 T137 1 T139 1
valid_sources[0x4a] 2901 1 T32 2 T138 1 T51 2
valid_sources[0x4b] 2726 1 T19 1 T138 1 T51 3
valid_sources[0x4c] 2776 1 T26 3 T30 1 T38 2
valid_sources[0x4d] 2321 1 T19 2 T34 3 T138 1
valid_sources[0x4e] 2925 1 T19 1 T32 1 T140 3
valid_sources[0x4f] 2615 1 T19 1 T137 1 T51 2
valid_sources[0x50] 3622 1 T137 1 T51 2 T52 4
valid_sources[0x51] 3353 1 T19 1 T137 1 T30 2
valid_sources[0x52] 2806 1 T26 3 T36 1 T30 1
valid_sources[0x53] 2493 1 T32 1 T30 1 T51 1
valid_sources[0x54] 2340 1 T51 2 T52 5 T53 33
valid_sources[0x55] 3040 1 T38 1 T52 2 T53 15
valid_sources[0x56] 2588 1 T137 1 T31 1 T51 5
valid_sources[0x57] 2643 1 T8 3 T138 2 T51 3
valid_sources[0x58] 2825 1 T34 1 T38 1 T51 6
valid_sources[0x59] 2699 1 T34 2 T31 1 T140 1
valid_sources[0x5a] 2904 1 T26 2 T32 1 T51 8
valid_sources[0x5b] 2807 1 T139 2 T36 1 T30 2
valid_sources[0x5c] 2705 1 T51 2 T52 14 T53 14
valid_sources[0x5d] 2893 1 T10 2 T30 1 T51 6
valid_sources[0x5e] 2689 1 T11 3 T142 1 T32 3
valid_sources[0x5f] 2951 1 T51 4 T52 7 T53 112
valid_sources[0x60] 2599 1 T51 1 T52 5 T53 23
valid_sources[0x61] 2936 1 T11 1 T137 1 T34 4
valid_sources[0x62] 2576 1 T26 3 T138 1 T43 1
valid_sources[0x63] 2595 1 T26 1 T137 1 T31 1
valid_sources[0x64] 2905 1 T10 1 T51 2 T52 2
valid_sources[0x65] 2569 1 T32 1 T51 1 T52 5
valid_sources[0x66] 4009 1 T137 1 T34 3 T31 4
valid_sources[0x67] 2575 1 T19 1 T136 1 T51 5
valid_sources[0x68] 2588 1 T8 2 T137 2 T141 1
valid_sources[0x69] 2452 1 T34 3 T51 3 T52 6
valid_sources[0x6a] 2915 1 T51 6 T52 3 T82 5
valid_sources[0x6b] 2463 1 T26 3 T30 1 T51 1
valid_sources[0x6c] 2692 1 T11 2 T20 14 T35 2
valid_sources[0x6d] 2290 1 T8 7 T19 1 T34 3
valid_sources[0x6e] 3032 1 T19 1 T30 1 T51 3
valid_sources[0x6f] 3050 1 T19 1 T11 1 T137 2
valid_sources[0x70] 2647 1 T19 1 T34 1 T31 7
valid_sources[0x71] 2917 1 T19 1 T142 1 T140 1
valid_sources[0x72] 2406 1 T139 1 T51 2 T52 1
valid_sources[0x73] 3195 1 T7 1 T26 1 T137 1
valid_sources[0x74] 2658 1 T32 2 T51 4 T53 13
valid_sources[0x75] 2482 1 T11 2 T34 2 T51 3
valid_sources[0x76] 2566 1 T8 2 T11 1 T141 1
valid_sources[0x77] 3059 1 T30 1 T51 4 T52 8
valid_sources[0x78] 2921 1 T19 1 T37 1 T139 1
valid_sources[0x79] 2469 1 T26 2 T51 5 T52 4
valid_sources[0x7a] 2318 1 T30 2 T143 2 T51 6
valid_sources[0x7b] 3084 1 T11 4 T36 1 T51 4
valid_sources[0x7c] 2757 1 T8 1 T51 3 T52 1
valid_sources[0x7d] 3036 1 T19 1 T11 1 T140 2
valid_sources[0x7e] 2866 1 T51 2 T52 8 T53 21
valid_sources[0x7f] 2933 1 T55 1 T51 5 T52 14
valid_sources[0x80] 2874 1 T34 2 T51 2 T52 10



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 265821 1 T4 3 T6 3 T8 7
values[0x0] all_enables biggest_size 136828 1 T3 6 T7 4 T4 2
values[0x1] all_enables biggest_size 136945 1 T3 2 T7 1 T4 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4261 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 24374 1 T21 2 T22 2 T39 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 9584 1 T51 33 T52 54 T53 33
values[0x0] 9296 1 T21 7 T22 6 T39 2
values[0x1] 9755 1 T21 5 T22 6 T39 2



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3235 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 25400 1 T21 5 T22 3 T39 2



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 115 1 T144 14 T71 1 T73 3
valid_sources[0x01] 98 1 T43 1 T93 1 T77 2
valid_sources[0x02] 84 1 T145 1 T43 1 T71 1
valid_sources[0x03] 116 1 T43 4 T93 1 T75 1
valid_sources[0x04] 125 1 T43 2 T73 2 T74 2
valid_sources[0x05] 107 1 T122 6 T146 1 T73 1
valid_sources[0x06] 116 1 T124 4 T43 5 T71 1
valid_sources[0x07] 90 1 T147 1 T148 1 T149 1
valid_sources[0x08] 89 1 T149 1 T150 1 T51 2
valid_sources[0x09] 120 1 T43 8 T74 8 T75 2
valid_sources[0x0a] 85 1 T71 1 T74 4 T93 3
valid_sources[0x0b] 97 1 T52 1 T43 2 T84 2
valid_sources[0x0c] 89 1 T71 1 T84 1 T74 4
valid_sources[0x0d] 105 1 T43 8 T71 1 T84 1
valid_sources[0x0e] 133 1 T43 1 T65 3 T74 2
valid_sources[0x0f] 127 1 T51 1 T43 9 T74 1
valid_sources[0x10] 83 1 T151 2 T43 2 T84 4
valid_sources[0x11] 119 1 T152 1 T74 2 T75 4
valid_sources[0x12] 128 1 T124 1 T51 1 T52 34
valid_sources[0x13] 111 1 T153 2 T154 1 T43 1
valid_sources[0x14] 104 1 T74 2 T93 1 T75 1
valid_sources[0x15] 124 1 T155 4 T43 6 T71 2
valid_sources[0x16] 127 1 T149 1 T51 2 T43 3
valid_sources[0x17] 106 1 T51 6 T52 6 T43 2
valid_sources[0x18] 94 1 T120 9 T156 1 T71 1
valid_sources[0x19] 103 1 T149 1 T51 1 T72 3
valid_sources[0x1a] 121 1 T43 9 T74 4 T90 3
valid_sources[0x1b] 112 1 T43 1 T84 1 T74 2
valid_sources[0x1c] 158 1 T52 1 T71 1 T84 2
valid_sources[0x1d] 108 1 T156 1 T71 1 T74 3
valid_sources[0x1e] 91 1 T43 4 T71 1 T77 1
valid_sources[0x1f] 110 1 T157 7 T158 4 T43 3
valid_sources[0x20] 126 1 T74 5 T93 1 T76 1
valid_sources[0x21] 102 1 T152 3 T43 1 T72 3
valid_sources[0x22] 108 1 T73 1 T74 1 T93 2
valid_sources[0x23] 102 1 T124 1 T73 1 T74 2
valid_sources[0x24] 134 1 T159 1 T151 1 T43 7
valid_sources[0x25] 89 1 T50 1 T122 1 T82 4
valid_sources[0x26] 100 1 T43 1 T71 2 T65 3
valid_sources[0x27] 105 1 T51 1 T43 1 T72 3
valid_sources[0x28] 99 1 T71 1 T74 1 T75 1
valid_sources[0x29] 136 1 T43 3 T71 1 T74 3
valid_sources[0x2a] 110 1 T81 1 T160 1 T53 3
valid_sources[0x2b] 113 1 T71 1 T72 3 T74 6
valid_sources[0x2c] 82 1 T145 1 T161 1 T51 3
valid_sources[0x2d] 103 1 T69 1 T71 2 T73 1
valid_sources[0x2e] 138 1 T151 1 T71 1 T73 1
valid_sources[0x2f] 99 1 T50 1 T75 1 T76 2
valid_sources[0x30] 122 1 T66 13 T67 3 T73 3
valid_sources[0x31] 84 1 T53 3 T84 3 T74 3
valid_sources[0x32] 121 1 T159 2 T43 3 T71 1
valid_sources[0x33] 109 1 T73 1 T74 2 T75 2
valid_sources[0x34] 82 1 T77 2 T90 2 T91 1
valid_sources[0x35] 99 1 T21 1 T162 4 T71 1
valid_sources[0x36] 122 1 T53 3 T43 5 T73 2
valid_sources[0x37] 78 1 T74 3 T93 1 T75 1
valid_sources[0x38] 95 1 T54 1 T148 1 T75 1
valid_sources[0x39] 132 1 T51 1 T52 9 T71 1
valid_sources[0x3a] 146 1 T83 4 T71 1 T72 3
valid_sources[0x3b] 130 1 T68 11 T148 1 T71 2
valid_sources[0x3c] 100 1 T50 1 T81 1 T163 3
valid_sources[0x3d] 110 1 T54 1 T52 1 T71 1
valid_sources[0x3e] 108 1 T164 1 T52 1 T43 7
valid_sources[0x3f] 120 1 T43 2 T71 1 T90 1
valid_sources[0x40] 110 1 T81 1 T160 1 T145 1
valid_sources[0x41] 96 1 T159 1 T84 1 T65 2
valid_sources[0x42] 124 1 T165 1 T73 1 T75 2
valid_sources[0x43] 75 1 T51 1 T43 2 T71 2
valid_sources[0x44] 109 1 T43 2 T71 2 T90 2
valid_sources[0x45] 105 1 T21 1 T52 1 T43 2
valid_sources[0x46] 93 1 T54 1 T163 1 T43 12
valid_sources[0x47] 99 1 T118 9 T146 1 T152 1
valid_sources[0x48] 125 1 T159 1 T151 1 T43 3
valid_sources[0x49] 86 1 T71 1 T84 2 T73 1
valid_sources[0x4a] 147 1 T148 1 T51 3 T43 4
valid_sources[0x4b] 101 1 T43 5 T71 1 T93 2
valid_sources[0x4c] 108 1 T71 1 T72 3 T73 1
valid_sources[0x4d] 122 1 T50 1 T145 1 T166 5
valid_sources[0x4e] 90 1 T43 1 T73 1 T74 5
valid_sources[0x4f] 85 1 T51 3 T72 3 T74 2
valid_sources[0x50] 79 1 T51 1 T71 1 T74 7
valid_sources[0x51] 94 1 T153 1 T43 2 T92 3
valid_sources[0x52] 127 1 T43 2 T74 2 T93 1
valid_sources[0x53] 89 1 T73 1 T74 2 T75 1
valid_sources[0x54] 93 1 T122 1 T43 1 T71 1
valid_sources[0x55] 106 1 T43 1 T72 3 T74 3
valid_sources[0x56] 157 1 T52 24 T43 9 T71 1
valid_sources[0x57] 102 1 T121 1 T71 1 T74 1
valid_sources[0x58] 105 1 T43 1 T82 6 T77 1
valid_sources[0x59] 107 1 T84 4 T74 1 T77 1
valid_sources[0x5a] 129 1 T43 1 T65 3 T77 2
valid_sources[0x5b] 119 1 T22 12 T52 11 T74 5
valid_sources[0x5c] 97 1 T43 6 T74 4 T75 1
valid_sources[0x5d] 103 1 T50 1 T150 1 T74 4
valid_sources[0x5e] 93 1 T163 1 T51 5 T74 3
valid_sources[0x5f] 118 1 T43 1 T82 4 T65 4
valid_sources[0x60] 102 1 T151 1 T53 3 T43 2
valid_sources[0x61] 132 1 T167 12 T52 3 T43 3
valid_sources[0x62] 199 1 T163 1 T43 1 T71 1
valid_sources[0x63] 75 1 T43 4 T71 1 T84 1
valid_sources[0x64] 114 1 T71 2 T74 2 T93 1
valid_sources[0x65] 109 1 T39 4 T50 1 T43 4
valid_sources[0x66] 112 1 T149 2 T43 1 T74 1
valid_sources[0x67] 88 1 T43 2 T76 1 T90 8
valid_sources[0x68] 128 1 T160 1 T51 4 T43 4
valid_sources[0x69] 131 1 T43 1 T71 1 T93 1
valid_sources[0x6a] 90 1 T43 1 T71 1 T92 1
valid_sources[0x6b] 114 1 T149 1 T43 3 T71 1
valid_sources[0x6c] 97 1 T43 7 T71 1 T72 3
valid_sources[0x6d] 106 1 T148 2 T168 1 T164 2
valid_sources[0x6e] 114 1 T54 1 T75 1 T76 1
valid_sources[0x6f] 146 1 T160 1 T51 5 T52 29
valid_sources[0x70] 134 1 T51 2 T53 3 T43 4
valid_sources[0x71] 143 1 T161 1 T53 39 T43 2
valid_sources[0x72] 127 1 T165 3 T51 1 T71 1
valid_sources[0x73] 152 1 T43 2 T65 26 T73 2
valid_sources[0x74] 89 1 T54 1 T165 1 T43 4
valid_sources[0x75] 97 1 T71 1 T74 2 T93 1
valid_sources[0x76] 114 1 T43 4 T71 1 T74 4
valid_sources[0x77] 121 1 T71 1 T73 1 T74 10
valid_sources[0x78] 107 1 T153 1 T72 3 T73 1
valid_sources[0x79] 80 1 T169 2 T161 1 T43 2
valid_sources[0x7a] 125 1 T43 2 T84 2 T77 2
valid_sources[0x7b] 76 1 T148 1 T74 1 T77 1
valid_sources[0x7c] 121 1 T51 1 T43 6 T73 1
valid_sources[0x7d] 130 1 T43 6 T74 1 T75 2
valid_sources[0x7e] 129 1 T74 1 T93 1 T76 1
valid_sources[0x7f] 89 1 T21 1 T156 1 T145 1
valid_sources[0x80] 130 1 T47 1 T43 9 T71 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7354 1 T51 29 T52 42 T53 12
values[0x0] all_enables biggest_size 8574 1 T21 2 T22 1 T39 2
values[0x1] all_enables biggest_size 8446 1 T22 1 T47 1 T50 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%