SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 756849 | 1 | T3 | 24 | T7 | 12 | T4 | 14 | |||
auto[1] | 27724 | 1 | T27 | 80 | T28 | 80 | T51 | 79 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 784355 | 1 | T3 | 24 | T7 | 12 | T4 | 14 | |||
values[1] | 28 | 1 | T65 | 1 | T92 | 1 | T93 | 1 | |||
values[2] | 2 | 1 | T127 | 1 | T128 | 1 | - | - | |||
values[3] | 116 | 1 | T53 | 3 | T65 | 1 | T72 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 784359 | 1 | T3 | 24 | T7 | 12 | T4 | 14 | |||
values[1] | 16 | 1 | T93 | 1 | T75 | 1 | T76 | 1 | |||
values[2] | 5 | 1 | T53 | 1 | T93 | 2 | T129 | 1 | |||
values[3] | 103 | 1 | T53 | 3 | T65 | 3 | T72 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 784263 | 1 | T3 | 24 | T7 | 12 | T4 | 14 | |||
auto[TlIntgErrCmd] | 96 | 1 | T53 | 2 | T65 | 3 | T72 | 4 | |||
auto[TlIntgErrData] | 92 | 1 | T53 | 5 | T65 | 4 | T72 | 6 | |||
auto[TlIntgErrBoth] | 122 | 1 | T53 | 3 | T65 | 3 | T72 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 53527 | 0 | T21 | 12 | T22 | 12 | T39 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 53325 | 1 | T21 | 12 | T22 | 12 | T39 | 4 | |||
values[1] | 27 | 1 | T65 | 1 | T72 | 1 | T92 | 1 | |||
values[2] | 5 | 1 | T93 | 1 | T76 | 2 | T78 | 2 | |||
values[3] | 95 | 1 | T53 | 3 | T65 | 3 | T72 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 53325 | 1 | T21 | 12 | T22 | 12 | T39 | 4 | |||
values[1] | 11 | 1 | T53 | 1 | T72 | 1 | T92 | 1 | |||
values[2] | 5 | 1 | T65 | 1 | T75 | 1 | T76 | 1 | |||
values[3] | 111 | 1 | T53 | 4 | T65 | 3 | T72 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 53217 | 1 | T21 | 12 | T22 | 12 | T39 | 4 | |||
auto[TlIntgErrCmd] | 108 | 1 | T53 | 5 | T65 | 2 | T72 | 7 | |||
auto[TlIntgErrData] | 108 | 1 | T53 | 4 | T65 | 4 | T72 | 4 | |||
auto[TlIntgErrBoth] | 94 | 1 | T53 | 1 | T65 | 4 | T72 | 9 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |