Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
242575 |
1 |
|
T3 |
16 |
|
T7 |
7 |
|
T4 |
8 |
full_word |
541998 |
1 |
|
T3 |
8 |
|
T7 |
5 |
|
T4 |
6 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
784263 |
1 |
|
T3 |
24 |
|
T7 |
12 |
|
T4 |
14 |
auto[TlIntgErrCmd] |
96 |
1 |
|
T53 |
2 |
|
T65 |
3 |
|
T72 |
4 |
auto[TlIntgErrData] |
92 |
1 |
|
T53 |
5 |
|
T65 |
4 |
|
T72 |
6 |
auto[TlIntgErrBoth] |
122 |
1 |
|
T53 |
3 |
|
T65 |
3 |
|
T72 |
10 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
443759 |
1 |
|
T4 |
6 |
|
T6 |
6 |
|
T8 |
12 |
auto[1] |
340814 |
1 |
|
T3 |
24 |
|
T7 |
12 |
|
T4 |
8 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
177560 |
1 |
|
T4 |
3 |
|
T6 |
3 |
|
T8 |
5 |
auto[TlIntgErrNone] |
partial |
auto[1] |
64738 |
1 |
|
T3 |
16 |
|
T7 |
7 |
|
T4 |
5 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
266058 |
1 |
|
T4 |
3 |
|
T6 |
3 |
|
T8 |
7 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
275907 |
1 |
|
T3 |
8 |
|
T7 |
5 |
|
T4 |
3 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
41 |
1 |
|
T53 |
1 |
|
T65 |
2 |
|
T72 |
2 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
46 |
1 |
|
T53 |
1 |
|
T65 |
1 |
|
T92 |
2 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
3 |
1 |
|
T130 |
1 |
|
T131 |
1 |
|
T132 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
6 |
1 |
|
T72 |
2 |
|
T131 |
1 |
|
T132 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
36 |
1 |
|
T53 |
1 |
|
T65 |
1 |
|
T72 |
1 |
auto[TlIntgErrData] |
partial |
auto[1] |
47 |
1 |
|
T53 |
4 |
|
T65 |
3 |
|
T72 |
4 |
auto[TlIntgErrData] |
full_word |
auto[0] |
6 |
1 |
|
T72 |
1 |
|
T92 |
1 |
|
T93 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
3 |
1 |
|
T76 |
1 |
|
T129 |
1 |
|
T133 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
47 |
1 |
|
T53 |
2 |
|
T65 |
2 |
|
T72 |
4 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
60 |
1 |
|
T53 |
1 |
|
T65 |
1 |
|
T72 |
6 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
8 |
1 |
|
T92 |
1 |
|
T75 |
1 |
|
T127 |
3 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
7 |
1 |
|
T75 |
1 |
|
T76 |
1 |
|
T78 |
1 |