Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.85	96.97	55.32	89.47		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	163634652	19877	0	0
late_debug_enable_rd_A	163634652	2450	0	0
late_debug_enable_regwen_rd_A	163634652	2539	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163634652	19877	0	0
T43	521089	145	0	0
T51	66543	33	0	0
T52	32845	411	0	0
T53	59734	2	0	0
T65	71353	1	0	0
T71	48276	35	0	0
T72	97244	3	0	0
T73	13240	21	0	0
T74	22053	494	0	0
T92	74893	4	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163634652	2450	0	0
T51	66543	24	0	0
T65	71353	6	0	0
T72	97244	32	0	0
T75	174193	47	0	0
T83	10566	2	0	0
T86	25329	20	0	0
T87	14368	1	0	0
T89	26954	9	0	0
T92	74893	48	0	0
T93	91000	85	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163634652	2539	0	0
T51	66543	49	0	0
T65	71353	20	0	0
T72	97244	54	0	0
T75	174193	43	0	0
T78	92837	46	0	0
T83	10566	8	0	0
T89	26954	3	0	0
T90	730371	400	0	0
T92	74893	45	0	0
T93	91000	126	0	0