Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 10857125 10855919 0 0
selKnown1 72735666 72734460 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 10857125 10855919 0 0
T1 30392 30388 0 0
T2 38074 38070 0 0
T3 23080 23076 0 0
T4 43602 43598 0 0
T5 8828 8824 0 0
T7 5898 5894 0 0
T8 0 15 0 0
T9 944 940 0 0
T12 21868 21864 0 0
T14 0 4 0 0
T16 0 26 0 0
T19 0 40 0 0
T21 222 218 0 0
T22 304 300 0 0
T23 0 2 0 0
T40 0 40 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 72735666 72734460 0 0
T1 461796 461792 0 0
T2 216436 216432 0 0
T3 92899 92895 0 0
T4 117931 117927 0 0
T5 99046 99042 0 0
T7 17855 17851 0 0
T8 0 6 0 0
T9 6344 6340 0 0
T12 272070 272066 0 0
T14 0 4 0 0
T16 0 10 0 0
T19 0 10 0 0
T21 1946 1942 0 0
T22 3906 3902 0 0
T23 0 2 0 0
T40 0 40 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 3350821 3350629 0 0
selKnown1 65229641 65229449 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 3350821 3350629 0 0
T1 15190 15189 0 0
T2 19029 19028 0 0
T3 11539 11538 0 0
T4 21793 21792 0 0
T5 4413 4412 0 0
T7 2948 2947 0 0
T9 471 470 0 0
T12 10932 10931 0 0
T21 110 109 0 0
T22 151 150 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 65229641 65229449 0 0
T1 446594 446593 0 0
T2 197391 197390 0 0
T3 81358 81357 0 0
T4 96128 96127 0 0
T5 94631 94630 0 0
T7 14905 14904 0 0
T9 5871 5870 0 0
T12 261134 261133 0 0
T21 1834 1833 0 0
T22 3753 3752 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 518 326 0 0
selKnown1 458 266 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 518 326 0 0
T1 6 5 0 0
T2 8 7 0 0
T3 1 0 0 0
T4 5 4 0 0
T5 1 0 0 0
T7 1 0 0 0
T8 0 7 0 0
T9 1 0 0 0
T12 2 1 0 0
T14 0 2 0 0
T16 0 9 0 0
T19 0 19 0 0
T21 1 0 0 0
T22 1 0 0 0
T23 0 1 0 0
T40 0 20 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 458 266 0 0
T1 6 5 0 0
T2 8 7 0 0
T3 1 0 0 0
T4 5 4 0 0
T5 1 0 0 0
T7 1 0 0 0
T8 0 3 0 0
T9 1 0 0 0
T12 2 1 0 0
T14 0 2 0 0
T16 0 5 0 0
T19 0 5 0 0
T21 1 0 0 0
T22 1 0 0 0
T23 0 1 0 0
T40 0 20 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 7504005 7503594 0 0
selKnown1 7504005 7503594 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 7504005 7503594 0 0
T1 15190 15189 0 0
T2 19029 19028 0 0
T3 11539 11538 0 0
T4 21793 21792 0 0
T5 4413 4412 0 0
T7 2948 2947 0 0
T9 471 470 0 0
T12 10932 10931 0 0
T21 110 109 0 0
T22 151 150 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 7504005 7503594 0 0
T1 15190 15189 0 0
T2 19029 19028 0 0
T3 11539 11538 0 0
T4 21793 21792 0 0
T5 4413 4412 0 0
T7 2948 2947 0 0
T9 471 470 0 0
T12 10932 10931 0 0
T21 110 109 0 0
T22 151 150 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1781 1370 0 0
selKnown1 1562 1151 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1781 1370 0 0
T1 6 5 0 0
T2 8 7 0 0
T3 1 0 0 0
T4 11 10 0 0
T5 1 0 0 0
T7 1 0 0 0
T8 0 8 0 0
T9 1 0 0 0
T12 2 1 0 0
T14 0 2 0 0
T16 0 17 0 0
T19 0 21 0 0
T21 1 0 0 0
T22 1 0 0 0
T23 0 1 0 0
T40 0 20 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1562 1151 0 0
T1 6 5 0 0
T2 8 7 0 0
T3 1 0 0 0
T4 5 4 0 0
T5 1 0 0 0
T7 1 0 0 0
T8 0 3 0 0
T9 1 0 0 0
T12 2 1 0 0
T14 0 2 0 0
T16 0 5 0 0
T19 0 5 0 0
T21 1 0 0 0
T22 1 0 0 0
T23 0 1 0 0
T40 0 20 0 0

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