Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.40 94.61 78.90 88.43 71.79 84.67 98.52 38.91


Total test records in report: 416
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T290 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2960728343 Jun 23 06:15:19 PM PDT 24 Jun 23 06:15:23 PM PDT 24 5807859480 ps
T291 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.351352398 Jun 23 06:14:27 PM PDT 24 Jun 23 06:14:28 PM PDT 24 733706711 ps
T109 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.145459493 Jun 23 06:14:36 PM PDT 24 Jun 23 06:14:41 PM PDT 24 1057473989 ps
T131 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.150798676 Jun 23 06:13:52 PM PDT 24 Jun 23 06:14:02 PM PDT 24 4076170226 ps
T292 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1816363062 Jun 23 06:14:57 PM PDT 24 Jun 23 06:15:10 PM PDT 24 16668990514 ps
T110 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1435106530 Jun 23 06:14:32 PM PDT 24 Jun 23 06:14:34 PM PDT 24 83761238 ps
T293 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.732066657 Jun 23 06:15:16 PM PDT 24 Jun 23 06:15:21 PM PDT 24 181909133 ps
T56 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1040716711 Jun 23 06:14:40 PM PDT 24 Jun 23 06:16:13 PM PDT 24 55908267210 ps
T294 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2881364561 Jun 23 06:14:40 PM PDT 24 Jun 23 06:14:43 PM PDT 24 164822506 ps
T101 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4216989507 Jun 23 06:14:08 PM PDT 24 Jun 23 06:14:18 PM PDT 24 7052656561 ps
T295 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.420978142 Jun 23 06:15:11 PM PDT 24 Jun 23 06:15:21 PM PDT 24 10766075108 ps
T296 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1532784507 Jun 23 06:14:57 PM PDT 24 Jun 23 06:14:59 PM PDT 24 474575033 ps
T297 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1311929987 Jun 23 06:13:59 PM PDT 24 Jun 23 06:14:00 PM PDT 24 1484909778 ps
T298 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.389256444 Jun 23 06:14:01 PM PDT 24 Jun 23 06:14:18 PM PDT 24 12314863952 ps
T111 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.543800258 Jun 23 06:14:40 PM PDT 24 Jun 23 06:14:43 PM PDT 24 493652120 ps
T299 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2283825205 Jun 23 06:15:04 PM PDT 24 Jun 23 06:15:10 PM PDT 24 2123402158 ps
T300 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1661338276 Jun 23 06:15:17 PM PDT 24 Jun 23 06:15:35 PM PDT 24 24344183291 ps
T301 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2792327823 Jun 23 06:14:36 PM PDT 24 Jun 23 06:14:39 PM PDT 24 3135992776 ps
T302 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3772921328 Jun 23 06:14:50 PM PDT 24 Jun 23 06:14:52 PM PDT 24 79293896 ps
T303 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1508925151 Jun 23 06:14:54 PM PDT 24 Jun 23 06:14:58 PM PDT 24 609407968 ps
T304 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1953180478 Jun 23 06:14:52 PM PDT 24 Jun 23 06:15:05 PM PDT 24 14193897354 ps
T129 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1865401392 Jun 23 06:14:08 PM PDT 24 Jun 23 06:14:39 PM PDT 24 5657661930 ps
T143 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3262680396 Jun 23 06:15:04 PM PDT 24 Jun 23 06:15:15 PM PDT 24 922606886 ps
T305 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2114491733 Jun 23 06:14:28 PM PDT 24 Jun 23 06:15:02 PM PDT 24 13900019297 ps
T306 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3946127786 Jun 23 06:14:18 PM PDT 24 Jun 23 06:14:20 PM PDT 24 57994214 ps
T144 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3842466005 Jun 23 06:14:37 PM PDT 24 Jun 23 06:15:00 PM PDT 24 47114695339 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2808557965 Jun 23 06:14:06 PM PDT 24 Jun 23 06:15:14 PM PDT 24 25532052604 ps
T136 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2267601356 Jun 23 06:14:47 PM PDT 24 Jun 23 06:14:58 PM PDT 24 946168083 ps
T308 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3732410576 Jun 23 06:15:05 PM PDT 24 Jun 23 06:15:15 PM PDT 24 3635321995 ps
T309 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2457584298 Jun 23 06:13:53 PM PDT 24 Jun 23 06:13:54 PM PDT 24 599773591 ps
T310 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1080316451 Jun 23 06:14:21 PM PDT 24 Jun 23 06:20:16 PM PDT 24 152142976817 ps
T311 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3755917114 Jun 23 06:14:52 PM PDT 24 Jun 23 06:14:57 PM PDT 24 203271728 ps
T312 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.378856717 Jun 23 06:14:53 PM PDT 24 Jun 23 06:14:56 PM PDT 24 2355466904 ps
T313 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3674999190 Jun 23 06:15:02 PM PDT 24 Jun 23 06:15:58 PM PDT 24 98517452776 ps
T314 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.743949602 Jun 23 06:14:01 PM PDT 24 Jun 23 06:14:03 PM PDT 24 158144886 ps
T315 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2191698873 Jun 23 06:14:43 PM PDT 24 Jun 23 06:14:48 PM PDT 24 2032104602 ps
T126 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1587415228 Jun 23 06:15:05 PM PDT 24 Jun 23 06:15:13 PM PDT 24 861366017 ps
T118 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4164384416 Jun 23 06:14:24 PM PDT 24 Jun 23 06:14:27 PM PDT 24 519104344 ps
T316 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3856815163 Jun 23 06:14:56 PM PDT 24 Jun 23 06:15:14 PM PDT 24 10769236497 ps
T119 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.162135404 Jun 23 06:14:33 PM PDT 24 Jun 23 06:14:35 PM PDT 24 115272242 ps
T317 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1400201780 Jun 23 06:14:26 PM PDT 24 Jun 23 06:14:59 PM PDT 24 23449229866 ps
T318 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1762620026 Jun 23 06:15:14 PM PDT 24 Jun 23 06:15:20 PM PDT 24 3730049294 ps
T319 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.741971703 Jun 23 06:14:29 PM PDT 24 Jun 23 06:14:34 PM PDT 24 4450335883 ps
T140 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3524778778 Jun 23 06:14:52 PM PDT 24 Jun 23 06:15:01 PM PDT 24 1887028218 ps
T141 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1965985117 Jun 23 06:14:57 PM PDT 24 Jun 23 06:15:23 PM PDT 24 6389748056 ps
T320 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2086737968 Jun 23 06:13:50 PM PDT 24 Jun 23 06:13:52 PM PDT 24 110115463 ps
T321 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1246651344 Jun 23 06:14:47 PM PDT 24 Jun 23 06:14:48 PM PDT 24 277314560 ps
T322 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.488117680 Jun 23 06:14:50 PM PDT 24 Jun 23 06:15:35 PM PDT 24 30825499618 ps
T323 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2219454132 Jun 23 06:15:02 PM PDT 24 Jun 23 06:15:04 PM PDT 24 225781300 ps
T127 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3862095682 Jun 23 06:14:08 PM PDT 24 Jun 23 06:14:13 PM PDT 24 1145059429 ps
T128 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1229480889 Jun 23 06:15:13 PM PDT 24 Jun 23 06:15:18 PM PDT 24 1433054245 ps
T112 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.113614062 Jun 23 06:15:01 PM PDT 24 Jun 23 06:15:04 PM PDT 24 81456591 ps
T113 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2649990100 Jun 23 06:13:50 PM PDT 24 Jun 23 06:13:57 PM PDT 24 254910027 ps
T114 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1044918253 Jun 23 06:15:12 PM PDT 24 Jun 23 06:15:16 PM PDT 24 3438226160 ps
T138 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1118641297 Jun 23 06:14:39 PM PDT 24 Jun 23 06:14:47 PM PDT 24 1404980628 ps
T324 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2023088323 Jun 23 06:14:32 PM PDT 24 Jun 23 06:14:33 PM PDT 24 68728786 ps
T120 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1312607492 Jun 23 06:14:22 PM PDT 24 Jun 23 06:14:24 PM PDT 24 519698734 ps
T325 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3890868490 Jun 23 06:14:11 PM PDT 24 Jun 23 06:14:48 PM PDT 24 3873833629 ps
T326 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3040417285 Jun 23 06:14:15 PM PDT 24 Jun 23 06:14:19 PM PDT 24 4349332698 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.586138983 Jun 23 06:14:30 PM PDT 24 Jun 23 06:14:42 PM PDT 24 18461043197 ps
T328 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2632984155 Jun 23 06:14:20 PM PDT 24 Jun 23 06:14:21 PM PDT 24 127529117 ps
T329 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.218602541 Jun 23 06:15:18 PM PDT 24 Jun 23 06:15:26 PM PDT 24 1131999422 ps
T330 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.463704346 Jun 23 06:15:08 PM PDT 24 Jun 23 06:15:10 PM PDT 24 318868078 ps
T102 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4130726402 Jun 23 06:14:31 PM PDT 24 Jun 23 06:14:38 PM PDT 24 2244217312 ps
T331 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4245242092 Jun 23 06:14:00 PM PDT 24 Jun 23 06:14:04 PM PDT 24 7151651951 ps
T332 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.179867389 Jun 23 06:15:15 PM PDT 24 Jun 23 06:15:17 PM PDT 24 632314590 ps
T333 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2796421978 Jun 23 06:14:42 PM PDT 24 Jun 23 06:14:49 PM PDT 24 2650592643 ps
T334 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2715605639 Jun 23 06:14:52 PM PDT 24 Jun 23 06:14:58 PM PDT 24 82890275 ps
T335 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4263224702 Jun 23 06:14:55 PM PDT 24 Jun 23 06:15:01 PM PDT 24 295464259 ps
T336 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.82002868 Jun 23 06:14:05 PM PDT 24 Jun 23 06:14:06 PM PDT 24 164318888 ps
T337 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.683109153 Jun 23 06:14:32 PM PDT 24 Jun 23 06:14:43 PM PDT 24 2024862110 ps
T338 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3142574690 Jun 23 06:15:20 PM PDT 24 Jun 23 06:15:21 PM PDT 24 249914745 ps
T339 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1366877801 Jun 23 06:14:44 PM PDT 24 Jun 23 06:14:56 PM PDT 24 3258521844 ps
T340 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2262651708 Jun 23 06:15:16 PM PDT 24 Jun 23 06:15:18 PM PDT 24 82763630 ps
T145 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3254080192 Jun 23 06:14:25 PM PDT 24 Jun 23 06:14:46 PM PDT 24 71572816298 ps
T341 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4004724638 Jun 23 06:14:24 PM PDT 24 Jun 23 06:14:25 PM PDT 24 483079164 ps
T342 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3788234651 Jun 23 06:13:48 PM PDT 24 Jun 23 06:13:49 PM PDT 24 200345342 ps
T121 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2614365828 Jun 23 06:14:58 PM PDT 24 Jun 23 06:15:01 PM PDT 24 62513610 ps
T343 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2477769920 Jun 23 06:15:18 PM PDT 24 Jun 23 06:15:21 PM PDT 24 195870755 ps
T344 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1509903902 Jun 23 06:13:50 PM PDT 24 Jun 23 06:14:13 PM PDT 24 20991227566 ps
T345 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2892806655 Jun 23 06:15:16 PM PDT 24 Jun 23 06:15:19 PM PDT 24 1454417013 ps
T346 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1134436115 Jun 23 06:14:48 PM PDT 24 Jun 23 06:15:45 PM PDT 24 81415704935 ps
T347 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4086441653 Jun 23 06:14:55 PM PDT 24 Jun 23 06:15:04 PM PDT 24 1242525298 ps
T348 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2881582625 Jun 23 06:14:11 PM PDT 24 Jun 23 06:14:14 PM PDT 24 889819920 ps
T349 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.614135867 Jun 23 06:14:23 PM PDT 24 Jun 23 06:14:25 PM PDT 24 546614720 ps
T350 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2297904103 Jun 23 06:14:56 PM PDT 24 Jun 23 06:15:00 PM PDT 24 206919106 ps
T351 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1988761212 Jun 23 06:13:47 PM PDT 24 Jun 23 06:16:02 PM PDT 24 56130616026 ps
T352 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2704151210 Jun 23 06:14:36 PM PDT 24 Jun 23 06:14:37 PM PDT 24 243472139 ps
T137 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1834271750 Jun 23 06:14:56 PM PDT 24 Jun 23 06:15:16 PM PDT 24 3849540144 ps
T353 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1868260483 Jun 23 06:15:17 PM PDT 24 Jun 23 06:15:20 PM PDT 24 59336456 ps
T354 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.913151010 Jun 23 06:13:52 PM PDT 24 Jun 23 06:13:53 PM PDT 24 84372958 ps
T115 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.670379287 Jun 23 06:13:53 PM PDT 24 Jun 23 06:14:58 PM PDT 24 1171114377 ps
T355 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2825634456 Jun 23 06:14:23 PM PDT 24 Jun 23 06:14:42 PM PDT 24 29459129188 ps
T356 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3481502449 Jun 23 06:15:06 PM PDT 24 Jun 23 06:15:10 PM PDT 24 6143744244 ps
T357 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2859725111 Jun 23 06:14:32 PM PDT 24 Jun 23 06:14:38 PM PDT 24 1006450543 ps
T134 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4181249896 Jun 23 06:15:16 PM PDT 24 Jun 23 06:15:30 PM PDT 24 2036026232 ps
T358 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2929207418 Jun 23 06:14:11 PM PDT 24 Jun 23 06:14:55 PM PDT 24 33646520500 ps
T359 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1032669313 Jun 23 06:14:01 PM PDT 24 Jun 23 06:14:02 PM PDT 24 51733021 ps
T360 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3801323348 Jun 23 06:14:00 PM PDT 24 Jun 23 06:15:44 PM PDT 24 154011426622 ps
T361 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2916602856 Jun 23 06:15:08 PM PDT 24 Jun 23 06:15:13 PM PDT 24 1067781260 ps
T362 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2934838456 Jun 23 06:14:50 PM PDT 24 Jun 23 06:14:51 PM PDT 24 431829397 ps
T363 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2923913506 Jun 23 06:14:55 PM PDT 24 Jun 23 06:15:45 PM PDT 24 18270107468 ps
T364 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1121269082 Jun 23 06:15:01 PM PDT 24 Jun 23 06:15:04 PM PDT 24 150856257 ps
T365 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2440890007 Jun 23 06:14:57 PM PDT 24 Jun 23 06:15:04 PM PDT 24 1604031399 ps
T366 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2566726370 Jun 23 06:14:14 PM PDT 24 Jun 23 06:14:17 PM PDT 24 104861280 ps
T142 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3636944926 Jun 23 06:13:52 PM PDT 24 Jun 23 06:14:23 PM PDT 24 5713276634 ps
T367 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2451823356 Jun 23 06:14:32 PM PDT 24 Jun 23 06:16:21 PM PDT 24 39016544412 ps
T139 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1082314361 Jun 23 06:14:56 PM PDT 24 Jun 23 06:15:07 PM PDT 24 3054711844 ps
T116 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4169857662 Jun 23 06:14:16 PM PDT 24 Jun 23 06:14:23 PM PDT 24 203041980 ps
T122 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2389500414 Jun 23 06:13:46 PM PDT 24 Jun 23 06:14:20 PM PDT 24 34093577955 ps
T368 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1321142833 Jun 23 06:14:55 PM PDT 24 Jun 23 06:15:04 PM PDT 24 538215268 ps
T369 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1568750918 Jun 23 06:15:15 PM PDT 24 Jun 23 06:15:25 PM PDT 24 8731333416 ps
T370 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1510410048 Jun 23 06:15:17 PM PDT 24 Jun 23 06:15:22 PM PDT 24 1699008064 ps
T371 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1243904111 Jun 23 06:14:40 PM PDT 24 Jun 23 06:14:43 PM PDT 24 144946224 ps
T372 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3759864702 Jun 23 06:14:50 PM PDT 24 Jun 23 06:17:02 PM PDT 24 50089477613 ps
T373 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.173804176 Jun 23 06:13:47 PM PDT 24 Jun 23 06:13:54 PM PDT 24 2718611622 ps
T374 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2086739006 Jun 23 06:14:12 PM PDT 24 Jun 23 06:15:26 PM PDT 24 79348444153 ps
T375 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1953618946 Jun 23 06:14:10 PM PDT 24 Jun 23 06:14:19 PM PDT 24 727284527 ps
T376 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3615353334 Jun 23 06:14:56 PM PDT 24 Jun 23 06:15:02 PM PDT 24 658379902 ps
T377 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.336827117 Jun 23 06:15:05 PM PDT 24 Jun 23 06:15:08 PM PDT 24 91042591 ps
T378 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2244504773 Jun 23 06:14:16 PM PDT 24 Jun 23 06:14:18 PM PDT 24 156769764 ps
T379 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3947174974 Jun 23 06:14:11 PM PDT 24 Jun 23 06:14:12 PM PDT 24 61822799 ps
T380 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.461816190 Jun 23 06:14:51 PM PDT 24 Jun 23 06:14:56 PM PDT 24 2297770070 ps
T381 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1666356129 Jun 23 06:14:52 PM PDT 24 Jun 23 06:14:53 PM PDT 24 62643348 ps
T123 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.996828120 Jun 23 06:14:49 PM PDT 24 Jun 23 06:14:52 PM PDT 24 148786719 ps
T382 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3957174132 Jun 23 06:14:23 PM PDT 24 Jun 23 06:14:31 PM PDT 24 6477166420 ps
T383 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3526308000 Jun 23 06:15:11 PM PDT 24 Jun 23 06:15:16 PM PDT 24 104837644 ps
T384 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2493855323 Jun 23 06:15:19 PM PDT 24 Jun 23 06:15:28 PM PDT 24 7046158436 ps
T385 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3205629336 Jun 23 06:14:48 PM PDT 24 Jun 23 06:14:50 PM PDT 24 184395686 ps
T135 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3902905730 Jun 23 06:15:12 PM PDT 24 Jun 23 06:15:24 PM PDT 24 1751668987 ps
T386 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1989171702 Jun 23 06:14:51 PM PDT 24 Jun 23 06:14:56 PM PDT 24 1459639634 ps
T387 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2064676175 Jun 23 06:14:53 PM PDT 24 Jun 23 06:14:54 PM PDT 24 1185479864 ps
T388 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1462318217 Jun 23 06:14:12 PM PDT 24 Jun 23 06:14:22 PM PDT 24 2874275151 ps
T389 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3726331430 Jun 23 06:14:57 PM PDT 24 Jun 23 06:14:59 PM PDT 24 161358620 ps
T117 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.761006401 Jun 23 06:15:01 PM PDT 24 Jun 23 06:15:06 PM PDT 24 1305469593 ps
T390 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.137608838 Jun 23 06:14:05 PM PDT 24 Jun 23 06:14:06 PM PDT 24 249609660 ps
T124 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.766785203 Jun 23 06:14:30 PM PDT 24 Jun 23 06:15:12 PM PDT 24 14730344447 ps
T391 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.690647075 Jun 23 06:14:58 PM PDT 24 Jun 23 06:15:03 PM PDT 24 2775048432 ps
T125 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.163114146 Jun 23 06:15:12 PM PDT 24 Jun 23 06:15:15 PM PDT 24 100237731 ps
T392 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.170335347 Jun 23 06:15:00 PM PDT 24 Jun 23 06:15:05 PM PDT 24 935785922 ps
T103 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1414671470 Jun 23 06:13:59 PM PDT 24 Jun 23 06:15:00 PM PDT 24 24174895928 ps
T393 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3084561950 Jun 23 06:14:55 PM PDT 24 Jun 23 06:14:58 PM PDT 24 365026782 ps
T394 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.282654833 Jun 23 06:15:02 PM PDT 24 Jun 23 06:15:13 PM PDT 24 2412763329 ps
T395 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3722913786 Jun 23 06:15:17 PM PDT 24 Jun 23 06:15:28 PM PDT 24 6843187143 ps
T396 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2835552091 Jun 23 06:13:47 PM PDT 24 Jun 23 06:13:53 PM PDT 24 2854631406 ps
T397 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2573837891 Jun 23 06:14:45 PM PDT 24 Jun 23 06:14:49 PM PDT 24 237428906 ps
T398 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.760219209 Jun 23 06:13:53 PM PDT 24 Jun 23 06:13:59 PM PDT 24 959837608 ps
T399 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2181829569 Jun 23 06:13:49 PM PDT 24 Jun 23 06:13:52 PM PDT 24 3635994318 ps
T400 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.662562788 Jun 23 06:14:32 PM PDT 24 Jun 23 06:14:33 PM PDT 24 88749704 ps
T401 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2251605399 Jun 23 06:14:21 PM PDT 24 Jun 23 06:14:24 PM PDT 24 649932500 ps
T402 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.878649038 Jun 23 06:14:42 PM PDT 24 Jun 23 06:14:45 PM PDT 24 169834164 ps
T403 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2472589343 Jun 23 06:15:08 PM PDT 24 Jun 23 06:15:17 PM PDT 24 3214081641 ps
T404 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3613057316 Jun 23 06:14:44 PM PDT 24 Jun 23 06:14:47 PM PDT 24 1430082772 ps
T405 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2663982665 Jun 23 06:15:13 PM PDT 24 Jun 23 06:15:15 PM PDT 24 442496362 ps
T406 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1785349899 Jun 23 06:13:54 PM PDT 24 Jun 23 06:13:56 PM PDT 24 128732227 ps
T407 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.630508158 Jun 23 06:15:05 PM PDT 24 Jun 23 06:15:07 PM PDT 24 1142218182 ps
T408 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2239432202 Jun 23 06:14:21 PM PDT 24 Jun 23 06:14:51 PM PDT 24 5299765079 ps
T409 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.293709621 Jun 23 06:13:45 PM PDT 24 Jun 23 06:13:46 PM PDT 24 116433703 ps
T410 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2436736470 Jun 23 06:13:55 PM PDT 24 Jun 23 06:13:56 PM PDT 24 141726682 ps
T411 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.630071579 Jun 23 06:13:51 PM PDT 24 Jun 23 06:13:59 PM PDT 24 2432628875 ps
T104 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2240768707 Jun 23 06:14:24 PM PDT 24 Jun 23 06:14:52 PM PDT 24 9260809464 ps
T412 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1508452706 Jun 23 06:14:50 PM PDT 24 Jun 23 06:14:56 PM PDT 24 2559618352 ps
T413 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4052630997 Jun 23 06:14:05 PM PDT 24 Jun 23 06:14:06 PM PDT 24 357043286 ps
T414 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2455344963 Jun 23 06:15:18 PM PDT 24 Jun 23 06:15:20 PM PDT 24 74043803 ps
T415 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3942010923 Jun 23 06:15:06 PM PDT 24 Jun 23 06:15:12 PM PDT 24 6024806328 ps
T416 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.833045531 Jun 23 06:15:07 PM PDT 24 Jun 23 06:15:10 PM PDT 24 164385078 ps

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1133337717
Short name T13
Test name
Test status
Simulation time 1753037971 ps
CPU time 2.27 seconds
Started Jun 23 06:00:51 PM PDT 24
Finished Jun 23 06:00:54 PM PDT 24
Peak memory 205128 kb
Host smart-f1ee81f9-f8d7-41ec-a297-20fdc92dd4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133337717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1133337717
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3579975301
Short name T54
Test name
Test status
Simulation time 62833141059 ps
CPU time 55.69 seconds
Started Jun 23 06:13:58 PM PDT 24
Finished Jun 23 06:14:54 PM PDT 24
Peak memory 223424 kb
Host smart-8534d56b-77ea-4c1d-8ee0-4e7026a19657
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579975301 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3579975301
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.236916706
Short name T16
Test name
Test status
Simulation time 40568987972 ps
CPU time 111.78 seconds
Started Jun 23 06:01:03 PM PDT 24
Finished Jun 23 06:02:55 PM PDT 24
Peak memory 213204 kb
Host smart-81cd64d7-aec3-4f22-8e01-7126a3c97c9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236916706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.236916706
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.35239915
Short name T32
Test name
Test status
Simulation time 80418098 ps
CPU time 0.71 seconds
Started Jun 23 06:00:54 PM PDT 24
Finished Jun 23 06:00:55 PM PDT 24
Peak memory 204804 kb
Host smart-1ceee5f7-e4f5-49df-b47b-7323bc0a7d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35239915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.35239915
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.4255561795
Short name T40
Test name
Test status
Simulation time 37617501610 ps
CPU time 17.76 seconds
Started Jun 23 06:01:26 PM PDT 24
Finished Jun 23 06:01:45 PM PDT 24
Peak memory 204988 kb
Host smart-f32be62b-3bd5-4dd7-8f03-0fbe5aee0fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255561795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.4255561795
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3772785054
Short name T74
Test name
Test status
Simulation time 4412371937 ps
CPU time 20.55 seconds
Started Jun 23 06:15:08 PM PDT 24
Finished Jun 23 06:15:29 PM PDT 24
Peak memory 213816 kb
Host smart-5ba4add5-ff59-44ff-82c3-eebe3256ffb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772785054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
772785054
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3502508278
Short name T193
Test name
Test status
Simulation time 134453525975 ps
CPU time 157.29 seconds
Started Jun 23 06:01:18 PM PDT 24
Finished Jun 23 06:03:55 PM PDT 24
Peak memory 221588 kb
Host smart-cbc358a8-12bf-416c-b780-04a5d66b7bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502508278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3502508278
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.1968522384
Short name T4
Test name
Test status
Simulation time 12195504300 ps
CPU time 16.69 seconds
Started Jun 23 06:01:31 PM PDT 24
Finished Jun 23 06:01:48 PM PDT 24
Peak memory 204960 kb
Host smart-e4d7279d-d3e7-43c9-8bbb-59ec4248090b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968522384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1968522384
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.125040902
Short name T12
Test name
Test status
Simulation time 22111346801 ps
CPU time 62.02 seconds
Started Jun 23 06:01:02 PM PDT 24
Finished Jun 23 06:02:05 PM PDT 24
Peak memory 204964 kb
Host smart-0792c5c3-fbad-4f4f-b04e-0fcafe33e6e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125040902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.125040902
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.549560985
Short name T106
Test name
Test status
Simulation time 14618466011 ps
CPU time 36.9 seconds
Started Jun 23 06:14:15 PM PDT 24
Finished Jun 23 06:14:53 PM PDT 24
Peak memory 213700 kb
Host smart-cc5bb70f-4c9a-4548-9781-5ca966da7379
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549560985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.549560985
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.830702388
Short name T52
Test name
Test status
Simulation time 581577675 ps
CPU time 1.54 seconds
Started Jun 23 06:00:42 PM PDT 24
Finished Jun 23 06:00:44 PM PDT 24
Peak memory 228300 kb
Host smart-cdeb55d2-afd2-41a2-87fa-476550e9678b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830702388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.830702388
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.670379287
Short name T115
Test name
Test status
Simulation time 1171114377 ps
CPU time 64.05 seconds
Started Jun 23 06:13:53 PM PDT 24
Finished Jun 23 06:14:58 PM PDT 24
Peak memory 213720 kb
Host smart-3b194243-0c9f-495c-9f0a-9250de38a61d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670379287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.670379287
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.933118647
Short name T42
Test name
Test status
Simulation time 265142159 ps
CPU time 1.17 seconds
Started Jun 23 06:00:12 PM PDT 24
Finished Jun 23 06:00:14 PM PDT 24
Peak memory 204708 kb
Host smart-0e84cad1-e919-4d8d-93eb-62dd1c94cfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933118647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.933118647
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3621992401
Short name T36
Test name
Test status
Simulation time 93866062 ps
CPU time 0.82 seconds
Started Jun 23 06:00:11 PM PDT 24
Finished Jun 23 06:00:12 PM PDT 24
Peak memory 213032 kb
Host smart-50e231b6-508d-4973-862f-4e6a292ce389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621992401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3621992401
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.280044804
Short name T6
Test name
Test status
Simulation time 159720645 ps
CPU time 0.96 seconds
Started Jun 23 06:00:04 PM PDT 24
Finished Jun 23 06:00:05 PM PDT 24
Peak memory 204780 kb
Host smart-cac5e7b2-bb5d-4621-a645-bef592466ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280044804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.280044804
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4043905763
Short name T62
Test name
Test status
Simulation time 867178412 ps
CPU time 4.08 seconds
Started Jun 23 06:14:52 PM PDT 24
Finished Jun 23 06:14:56 PM PDT 24
Peak memory 205380 kb
Host smart-8579c474-0a88-468a-8447-e03c7ee9ef9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043905763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.4043905763
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1419138997
Short name T48
Test name
Test status
Simulation time 254085649 ps
CPU time 0.9 seconds
Started Jun 23 06:00:14 PM PDT 24
Finished Jun 23 06:00:15 PM PDT 24
Peak memory 204764 kb
Host smart-65071e85-7d3a-492d-b864-74dfff9181da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419138997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1419138997
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.368663801
Short name T83
Test name
Test status
Simulation time 4309345127 ps
CPU time 26.35 seconds
Started Jun 23 06:13:59 PM PDT 24
Finished Jun 23 06:14:26 PM PDT 24
Peak memory 213832 kb
Host smart-4303b8dd-4cf6-45be-8fb9-6a273dc398ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368663801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.368663801
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1834271750
Short name T137
Test name
Test status
Simulation time 3849540144 ps
CPU time 19.88 seconds
Started Jun 23 06:14:56 PM PDT 24
Finished Jun 23 06:15:16 PM PDT 24
Peak memory 213796 kb
Host smart-5194b632-2131-47c7-ba6c-d75fc5679922
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834271750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
834271750
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2881364561
Short name T294
Test name
Test status
Simulation time 164822506 ps
CPU time 2.76 seconds
Started Jun 23 06:14:40 PM PDT 24
Finished Jun 23 06:14:43 PM PDT 24
Peak memory 216180 kb
Host smart-1ca72024-8a46-40c6-b269-f88ed6bb17c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881364561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2881364561
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.4065800146
Short name T180
Test name
Test status
Simulation time 35962797 ps
CPU time 0.77 seconds
Started Jun 23 06:00:32 PM PDT 24
Finished Jun 23 06:00:33 PM PDT 24
Peak memory 204848 kb
Host smart-52ee925a-fb8e-43de-bc91-786831957a6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065800146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4065800146
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1311929987
Short name T297
Test name
Test status
Simulation time 1484909778 ps
CPU time 1.03 seconds
Started Jun 23 06:13:59 PM PDT 24
Finished Jun 23 06:14:00 PM PDT 24
Peak memory 205120 kb
Host smart-d91756ad-17db-4ad9-9d01-123a4d6f3d2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311929987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1311929987
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1414671470
Short name T103
Test name
Test status
Simulation time 24174895928 ps
CPU time 60.47 seconds
Started Jun 23 06:13:59 PM PDT 24
Finished Jun 23 06:15:00 PM PDT 24
Peak memory 213860 kb
Host smart-a148aed0-5d39-48a2-9334-bb9a43c3218b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414671470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1414671470
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3452178440
Short name T34
Test name
Test status
Simulation time 248830137 ps
CPU time 1.39 seconds
Started Jun 23 06:00:02 PM PDT 24
Finished Jun 23 06:00:04 PM PDT 24
Peak memory 204568 kb
Host smart-fa6d9f93-858d-4984-98bd-cf954f111db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452178440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3452178440
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.62722308
Short name T41
Test name
Test status
Simulation time 622484051 ps
CPU time 2.37 seconds
Started Jun 23 06:00:09 PM PDT 24
Finished Jun 23 06:00:12 PM PDT 24
Peak memory 204752 kb
Host smart-cd3a0b80-e0b3-4197-9ed5-9f8767db2868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62722308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.62722308
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3636944926
Short name T142
Test name
Test status
Simulation time 5713276634 ps
CPU time 31.19 seconds
Started Jun 23 06:13:52 PM PDT 24
Finished Jun 23 06:14:23 PM PDT 24
Peak memory 221944 kb
Host smart-d6e5b2e2-2b43-4e13-af54-e9e217c82e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636944926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3636944926
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3902905730
Short name T135
Test name
Test status
Simulation time 1751668987 ps
CPU time 11.79 seconds
Started Jun 23 06:15:12 PM PDT 24
Finished Jun 23 06:15:24 PM PDT 24
Peak memory 213708 kb
Host smart-9eecc054-fd9c-4537-8fa8-2bd1410bb3c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902905730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
902905730
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3254080192
Short name T145
Test name
Test status
Simulation time 71572816298 ps
CPU time 19.97 seconds
Started Jun 23 06:14:25 PM PDT 24
Finished Jun 23 06:14:46 PM PDT 24
Peak memory 232476 kb
Host smart-99347d7e-e921-4b60-932a-c3c13923f67a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254080192 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3254080192
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2389500414
Short name T122
Test name
Test status
Simulation time 34093577955 ps
CPU time 34.47 seconds
Started Jun 23 06:13:46 PM PDT 24
Finished Jun 23 06:14:20 PM PDT 24
Peak memory 205588 kb
Host smart-448e86f8-1eee-4267-adfa-0ee4bba81a13
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389500414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2389500414
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2189929025
Short name T90
Test name
Test status
Simulation time 2823150218 ps
CPU time 31.77 seconds
Started Jun 23 06:13:52 PM PDT 24
Finished Jun 23 06:14:24 PM PDT 24
Peak memory 205752 kb
Host smart-495e91f9-70bb-46af-92c8-23d55b380f33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189929025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2189929025
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2086737968
Short name T320
Test name
Test status
Simulation time 110115463 ps
CPU time 1.61 seconds
Started Jun 23 06:13:50 PM PDT 24
Finished Jun 23 06:13:52 PM PDT 24
Peak memory 213740 kb
Host smart-55b8ee42-dca0-4a04-ac92-1ee9c675be22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086737968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2086737968
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.150798676
Short name T131
Test name
Test status
Simulation time 4076170226 ps
CPU time 10.43 seconds
Started Jun 23 06:13:52 PM PDT 24
Finished Jun 23 06:14:02 PM PDT 24
Peak memory 220192 kb
Host smart-9d9e6646-5d1c-4685-b4ac-908ed812b2d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150798676 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.150798676
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1785349899
Short name T406
Test name
Test status
Simulation time 128732227 ps
CPU time 2.5 seconds
Started Jun 23 06:13:54 PM PDT 24
Finished Jun 23 06:13:56 PM PDT 24
Peak memory 213672 kb
Host smart-4479bd18-be06-4202-a320-f69ba4907075
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785349899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1785349899
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2775364323
Short name T277
Test name
Test status
Simulation time 45174094597 ps
CPU time 29.72 seconds
Started Jun 23 06:13:49 PM PDT 24
Finished Jun 23 06:14:19 PM PDT 24
Peak memory 205480 kb
Host smart-685a5d47-7e4e-4171-a571-0e987580ac70
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775364323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2775364323
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.630071579
Short name T411
Test name
Test status
Simulation time 2432628875 ps
CPU time 7.47 seconds
Started Jun 23 06:13:51 PM PDT 24
Finished Jun 23 06:13:59 PM PDT 24
Peak memory 205436 kb
Host smart-0166ad28-83b4-4483-b65b-4198e5952fec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630071579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
v_dm_jtag_dmi_csr_bit_bash.630071579
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.173804176
Short name T373
Test name
Test status
Simulation time 2718611622 ps
CPU time 6.98 seconds
Started Jun 23 06:13:47 PM PDT 24
Finished Jun 23 06:13:54 PM PDT 24
Peak memory 205480 kb
Host smart-55e6e55a-defc-4a33-bb22-d15bc918572e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173804176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.173804176
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2181829569
Short name T399
Test name
Test status
Simulation time 3635994318 ps
CPU time 2.64 seconds
Started Jun 23 06:13:49 PM PDT 24
Finished Jun 23 06:13:52 PM PDT 24
Peak memory 205464 kb
Host smart-7216317a-fc5d-4d89-9886-81b2e5c7caf5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181829569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
181829569
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2835552091
Short name T396
Test name
Test status
Simulation time 2854631406 ps
CPU time 5.32 seconds
Started Jun 23 06:13:47 PM PDT 24
Finished Jun 23 06:13:53 PM PDT 24
Peak memory 205264 kb
Host smart-ccf41b67-6b53-4ab8-ab01-af505ed16d4f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835552091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2835552091
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1509903902
Short name T344
Test name
Test status
Simulation time 20991227566 ps
CPU time 23 seconds
Started Jun 23 06:13:50 PM PDT 24
Finished Jun 23 06:14:13 PM PDT 24
Peak memory 205436 kb
Host smart-0f7df27c-e852-4a4b-b147-b871312d2260
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509903902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1509903902
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.293709621
Short name T409
Test name
Test status
Simulation time 116433703 ps
CPU time 0.78 seconds
Started Jun 23 06:13:45 PM PDT 24
Finished Jun 23 06:13:46 PM PDT 24
Peak memory 205176 kb
Host smart-cca66e3e-d6f3-4f00-aa11-d2a30c00cd70
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293709621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.293709621
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3788234651
Short name T342
Test name
Test status
Simulation time 200345342 ps
CPU time 0.79 seconds
Started Jun 23 06:13:48 PM PDT 24
Finished Jun 23 06:13:49 PM PDT 24
Peak memory 205168 kb
Host smart-7f2dc081-49df-4828-bf02-6bfce8481630
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788234651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
788234651
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.913151010
Short name T354
Test name
Test status
Simulation time 84372958 ps
CPU time 0.79 seconds
Started Jun 23 06:13:52 PM PDT 24
Finished Jun 23 06:13:53 PM PDT 24
Peak memory 205292 kb
Host smart-ab5fdac2-99c7-4e9c-91f6-10eff5327335
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913151010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.913151010
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2436736470
Short name T410
Test name
Test status
Simulation time 141726682 ps
CPU time 1.03 seconds
Started Jun 23 06:13:55 PM PDT 24
Finished Jun 23 06:13:56 PM PDT 24
Peak memory 205172 kb
Host smart-d90b840c-93b8-4f60-8a7c-53a1d2c6e55d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436736470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2436736470
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2649990100
Short name T113
Test name
Test status
Simulation time 254910027 ps
CPU time 6.71 seconds
Started Jun 23 06:13:50 PM PDT 24
Finished Jun 23 06:13:57 PM PDT 24
Peak memory 205484 kb
Host smart-48c5d909-bddc-450f-bdb4-46a4fc64c6ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649990100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2649990100
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1988761212
Short name T351
Test name
Test status
Simulation time 56130616026 ps
CPU time 134.63 seconds
Started Jun 23 06:13:47 PM PDT 24
Finished Jun 23 06:16:02 PM PDT 24
Peak memory 223696 kb
Host smart-452f9f38-9c8a-4b8e-8338-bbe0fbf608e5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988761212 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1988761212
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.760219209
Short name T398
Test name
Test status
Simulation time 959837608 ps
CPU time 5.49 seconds
Started Jun 23 06:13:53 PM PDT 24
Finished Jun 23 06:13:59 PM PDT 24
Peak memory 213944 kb
Host smart-4c00d447-dce0-4fd4-9334-3716dd946542
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760219209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.760219209
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3890868490
Short name T325
Test name
Test status
Simulation time 3873833629 ps
CPU time 36.64 seconds
Started Jun 23 06:14:11 PM PDT 24
Finished Jun 23 06:14:48 PM PDT 24
Peak memory 213716 kb
Host smart-769cdc52-df37-480d-b0eb-f99f31dab991
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890868490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3890868490
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.82002868
Short name T336
Test name
Test status
Simulation time 164318888 ps
CPU time 1.71 seconds
Started Jun 23 06:14:05 PM PDT 24
Finished Jun 23 06:14:06 PM PDT 24
Peak memory 213696 kb
Host smart-986103f1-f035-4b9c-937e-cddda7ce04b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82002868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.82002868
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2047862400
Short name T130
Test name
Test status
Simulation time 3412580299 ps
CPU time 5.52 seconds
Started Jun 23 06:14:11 PM PDT 24
Finished Jun 23 06:14:17 PM PDT 24
Peak memory 221860 kb
Host smart-23d17c60-5352-49db-bedb-87de83d54a28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047862400 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2047862400
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2818312021
Short name T85
Test name
Test status
Simulation time 159065620 ps
CPU time 1.55 seconds
Started Jun 23 06:14:09 PM PDT 24
Finished Jun 23 06:14:11 PM PDT 24
Peak memory 213596 kb
Host smart-58663988-543b-4044-8fa4-0e9ce4279cc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818312021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2818312021
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3801323348
Short name T360
Test name
Test status
Simulation time 154011426622 ps
CPU time 104.69 seconds
Started Jun 23 06:14:00 PM PDT 24
Finished Jun 23 06:15:44 PM PDT 24
Peak memory 206816 kb
Host smart-6c067c39-0e12-4c00-8207-bce1c648121e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801323348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3801323348
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1027670385
Short name T281
Test name
Test status
Simulation time 15551722560 ps
CPU time 13.59 seconds
Started Jun 23 06:14:01 PM PDT 24
Finished Jun 23 06:14:15 PM PDT 24
Peak memory 205480 kb
Host smart-c0c6b634-15e5-471c-895b-4f12004d6e56
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027670385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1027670385
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4245242092
Short name T331
Test name
Test status
Simulation time 7151651951 ps
CPU time 4.06 seconds
Started Jun 23 06:14:00 PM PDT 24
Finished Jun 23 06:14:04 PM PDT 24
Peak memory 205468 kb
Host smart-869c72e7-3278-4efb-93d9-3a328d07fd7a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245242092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4
245242092
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.389256444
Short name T298
Test name
Test status
Simulation time 12314863952 ps
CPU time 16.86 seconds
Started Jun 23 06:14:01 PM PDT 24
Finished Jun 23 06:14:18 PM PDT 24
Peak memory 205540 kb
Host smart-f4be7e86-5f57-4645-b53b-3d9acd18e185
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389256444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.389256444
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2457584298
Short name T309
Test name
Test status
Simulation time 599773591 ps
CPU time 1.09 seconds
Started Jun 23 06:13:53 PM PDT 24
Finished Jun 23 06:13:54 PM PDT 24
Peak memory 205184 kb
Host smart-3ba38070-90aa-4533-a227-40f3001224aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457584298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2457584298
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.743949602
Short name T314
Test name
Test status
Simulation time 158144886 ps
CPU time 1.07 seconds
Started Jun 23 06:14:01 PM PDT 24
Finished Jun 23 06:14:03 PM PDT 24
Peak memory 205160 kb
Host smart-9dd3dc1b-7f9d-422b-814f-43efbf643d75
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743949602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.743949602
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3947174974
Short name T379
Test name
Test status
Simulation time 61822799 ps
CPU time 0.73 seconds
Started Jun 23 06:14:11 PM PDT 24
Finished Jun 23 06:14:12 PM PDT 24
Peak memory 205004 kb
Host smart-d732ec79-43bd-4337-b792-058db8f0b4d2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947174974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3947174974
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1032669313
Short name T359
Test name
Test status
Simulation time 51733021 ps
CPU time 0.71 seconds
Started Jun 23 06:14:01 PM PDT 24
Finished Jun 23 06:14:02 PM PDT 24
Peak memory 205324 kb
Host smart-dafd91e5-f950-4ac0-a253-7496bf7c86ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032669313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1032669313
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3862095682
Short name T127
Test name
Test status
Simulation time 1145059429 ps
CPU time 4.36 seconds
Started Jun 23 06:14:08 PM PDT 24
Finished Jun 23 06:14:13 PM PDT 24
Peak memory 205484 kb
Host smart-a259fdff-29a9-4cce-8045-a9348e973e42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862095682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3862095682
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2146888367
Short name T80
Test name
Test status
Simulation time 140903674 ps
CPU time 2.57 seconds
Started Jun 23 06:14:04 PM PDT 24
Finished Jun 23 06:14:07 PM PDT 24
Peak memory 213660 kb
Host smart-a51e81d6-1d22-4dca-890b-cb3637b1e0b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146888367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2146888367
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3608657648
Short name T289
Test name
Test status
Simulation time 6872591122 ps
CPU time 5.95 seconds
Started Jun 23 06:14:57 PM PDT 24
Finished Jun 23 06:15:04 PM PDT 24
Peak memory 219468 kb
Host smart-50106831-c122-424a-beb3-ac62c2b2e2ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608657648 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3608657648
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3084561950
Short name T393
Test name
Test status
Simulation time 365026782 ps
CPU time 1.69 seconds
Started Jun 23 06:14:55 PM PDT 24
Finished Jun 23 06:14:58 PM PDT 24
Peak memory 213688 kb
Host smart-6417994f-097b-48a9-bda0-4dddf7e21e4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084561950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3084561950
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2923913506
Short name T363
Test name
Test status
Simulation time 18270107468 ps
CPU time 49.11 seconds
Started Jun 23 06:14:55 PM PDT 24
Finished Jun 23 06:15:45 PM PDT 24
Peak memory 205428 kb
Host smart-934e1294-492c-4174-8ae3-3720e169db42
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923913506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2923913506
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1989171702
Short name T386
Test name
Test status
Simulation time 1459639634 ps
CPU time 4.59 seconds
Started Jun 23 06:14:51 PM PDT 24
Finished Jun 23 06:14:56 PM PDT 24
Peak memory 205356 kb
Host smart-0a1796c8-2220-4566-a4f5-63a31aa8bb37
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989171702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1989171702
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1708139351
Short name T287
Test name
Test status
Simulation time 253798396 ps
CPU time 0.8 seconds
Started Jun 23 06:14:52 PM PDT 24
Finished Jun 23 06:14:53 PM PDT 24
Peak memory 205160 kb
Host smart-0aa89c30-bb5c-4bb1-960f-b83792502f20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708139351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1708139351
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.690647075
Short name T391
Test name
Test status
Simulation time 2775048432 ps
CPU time 4.66 seconds
Started Jun 23 06:14:58 PM PDT 24
Finished Jun 23 06:15:03 PM PDT 24
Peak memory 205600 kb
Host smart-335c271a-2539-446a-8fa9-ffebd57028f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690647075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.690647075
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2715605639
Short name T334
Test name
Test status
Simulation time 82890275 ps
CPU time 5.21 seconds
Started Jun 23 06:14:52 PM PDT 24
Finished Jun 23 06:14:58 PM PDT 24
Peak memory 213808 kb
Host smart-1a90ebd9-7c98-4d54-92d5-442406071a4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715605639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2715605639
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2440890007
Short name T365
Test name
Test status
Simulation time 1604031399 ps
CPU time 6.17 seconds
Started Jun 23 06:14:57 PM PDT 24
Finished Jun 23 06:15:04 PM PDT 24
Peak memory 219640 kb
Host smart-091ec2b2-3d81-4390-81ce-a3717cd09152
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440890007 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2440890007
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2297904103
Short name T350
Test name
Test status
Simulation time 206919106 ps
CPU time 2.43 seconds
Started Jun 23 06:14:56 PM PDT 24
Finished Jun 23 06:15:00 PM PDT 24
Peak memory 213652 kb
Host smart-1600807c-8cd4-4dfc-b778-eab0b5f3dac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297904103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2297904103
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3866624963
Short name T273
Test name
Test status
Simulation time 11563138638 ps
CPU time 4.72 seconds
Started Jun 23 06:14:57 PM PDT 24
Finished Jun 23 06:15:02 PM PDT 24
Peak memory 205428 kb
Host smart-3f7aa545-90be-454f-93bd-a83ab90cb548
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866624963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3866624963
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3856815163
Short name T316
Test name
Test status
Simulation time 10769236497 ps
CPU time 16.53 seconds
Started Jun 23 06:14:56 PM PDT 24
Finished Jun 23 06:15:14 PM PDT 24
Peak memory 205484 kb
Host smart-5a421e44-dac8-4046-9057-b3e053fb3da4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856815163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3856815163
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3726331430
Short name T389
Test name
Test status
Simulation time 161358620 ps
CPU time 1.15 seconds
Started Jun 23 06:14:57 PM PDT 24
Finished Jun 23 06:14:59 PM PDT 24
Peak memory 205140 kb
Host smart-7aacc4c3-57fd-4b51-a25b-dbfde97d2616
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726331430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3726331430
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1321142833
Short name T368
Test name
Test status
Simulation time 538215268 ps
CPU time 8.06 seconds
Started Jun 23 06:14:55 PM PDT 24
Finished Jun 23 06:15:04 PM PDT 24
Peak memory 205484 kb
Host smart-35ffbac1-4aa9-444d-ada8-65a40ce9d3ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321142833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1321142833
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3615353334
Short name T376
Test name
Test status
Simulation time 658379902 ps
CPU time 5.4 seconds
Started Jun 23 06:14:56 PM PDT 24
Finished Jun 23 06:15:02 PM PDT 24
Peak memory 213768 kb
Host smart-f9009242-3f69-48a4-8a2c-69ac964633e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615353334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3615353334
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1082314361
Short name T139
Test name
Test status
Simulation time 3054711844 ps
CPU time 10.75 seconds
Started Jun 23 06:14:56 PM PDT 24
Finished Jun 23 06:15:07 PM PDT 24
Peak memory 213684 kb
Host smart-269bd11e-8c08-4dc6-9eb7-0d1b0b832e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082314361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
082314361
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3635558556
Short name T82
Test name
Test status
Simulation time 247588583 ps
CPU time 3.51 seconds
Started Jun 23 06:14:57 PM PDT 24
Finished Jun 23 06:15:01 PM PDT 24
Peak memory 218956 kb
Host smart-b22bd3e6-d856-44ac-a0f1-16d7f27e4b21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635558556 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3635558556
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1304085492
Short name T107
Test name
Test status
Simulation time 552972735 ps
CPU time 2.69 seconds
Started Jun 23 06:14:56 PM PDT 24
Finished Jun 23 06:14:59 PM PDT 24
Peak memory 213632 kb
Host smart-47865241-c381-48a0-8c24-b7457f24237c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304085492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1304085492
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3325718110
Short name T271
Test name
Test status
Simulation time 20422107070 ps
CPU time 28.71 seconds
Started Jun 23 06:14:58 PM PDT 24
Finished Jun 23 06:15:27 PM PDT 24
Peak memory 205436 kb
Host smart-0cab231f-4ea0-4a06-9256-461744d2f98b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325718110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3325718110
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1816363062
Short name T292
Test name
Test status
Simulation time 16668990514 ps
CPU time 12.58 seconds
Started Jun 23 06:14:57 PM PDT 24
Finished Jun 23 06:15:10 PM PDT 24
Peak memory 205448 kb
Host smart-693619d5-4340-49ae-8c4d-547a5ae5dc48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816363062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1816363062
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1532784507
Short name T296
Test name
Test status
Simulation time 474575033 ps
CPU time 1.43 seconds
Started Jun 23 06:14:57 PM PDT 24
Finished Jun 23 06:14:59 PM PDT 24
Peak memory 204060 kb
Host smart-60ca630b-f231-42d5-b7c5-dd12c2fe6b2d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532784507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1532784507
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.761006401
Short name T117
Test name
Test status
Simulation time 1305469593 ps
CPU time 3.77 seconds
Started Jun 23 06:15:01 PM PDT 24
Finished Jun 23 06:15:06 PM PDT 24
Peak memory 205496 kb
Host smart-1df95b05-878b-4791-9fd7-811447554a99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761006401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.761006401
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4263224702
Short name T335
Test name
Test status
Simulation time 295464259 ps
CPU time 4.79 seconds
Started Jun 23 06:14:55 PM PDT 24
Finished Jun 23 06:15:01 PM PDT 24
Peak memory 213748 kb
Host smart-713a6e27-cb16-45f4-93a4-e023fdf2cbf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263224702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4263224702
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1965985117
Short name T141
Test name
Test status
Simulation time 6389748056 ps
CPU time 25.71 seconds
Started Jun 23 06:14:57 PM PDT 24
Finished Jun 23 06:15:23 PM PDT 24
Peak memory 213844 kb
Host smart-8fe9fab5-c0c2-45d1-8cf9-688e2fdc3ae3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965985117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
965985117
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2421108638
Short name T60
Test name
Test status
Simulation time 4574838580 ps
CPU time 7.17 seconds
Started Jun 23 06:15:06 PM PDT 24
Finished Jun 23 06:15:13 PM PDT 24
Peak memory 219716 kb
Host smart-8126dacd-bfd4-485a-84a2-220c7dfe8b76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421108638 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2421108638
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.113614062
Short name T112
Test name
Test status
Simulation time 81456591 ps
CPU time 2.14 seconds
Started Jun 23 06:15:01 PM PDT 24
Finished Jun 23 06:15:04 PM PDT 24
Peak memory 213680 kb
Host smart-03bd0242-4b82-4041-b2bc-4bbd583f08b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113614062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.113614062
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3674999190
Short name T313
Test name
Test status
Simulation time 98517452776 ps
CPU time 56.27 seconds
Started Jun 23 06:15:02 PM PDT 24
Finished Jun 23 06:15:58 PM PDT 24
Peak memory 205432 kb
Host smart-23f3b483-b071-4a83-9d5a-69a79f0d24aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674999190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3674999190
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3481502449
Short name T356
Test name
Test status
Simulation time 6143744244 ps
CPU time 3.52 seconds
Started Jun 23 06:15:06 PM PDT 24
Finished Jun 23 06:15:10 PM PDT 24
Peak memory 205436 kb
Host smart-578d4a07-4613-43fe-bc1d-872964b3900b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481502449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3481502449
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2219454132
Short name T323
Test name
Test status
Simulation time 225781300 ps
CPU time 1.25 seconds
Started Jun 23 06:15:02 PM PDT 24
Finished Jun 23 06:15:04 PM PDT 24
Peak memory 205168 kb
Host smart-d696c5b0-64ce-4375-bd08-ce8a8f85544d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219454132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2219454132
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.170335347
Short name T392
Test name
Test status
Simulation time 935785922 ps
CPU time 4.36 seconds
Started Jun 23 06:15:00 PM PDT 24
Finished Jun 23 06:15:05 PM PDT 24
Peak memory 205544 kb
Host smart-de02f2e2-7c28-45e8-adf0-f03fba91ea40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170335347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.170335347
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2413342426
Short name T99
Test name
Test status
Simulation time 70145662 ps
CPU time 3.1 seconds
Started Jun 23 06:15:04 PM PDT 24
Finished Jun 23 06:15:08 PM PDT 24
Peak memory 213804 kb
Host smart-7b2eced6-3d50-45a7-ad21-5627edf7a56c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413342426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2413342426
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3262680396
Short name T143
Test name
Test status
Simulation time 922606886 ps
CPU time 10.55 seconds
Started Jun 23 06:15:04 PM PDT 24
Finished Jun 23 06:15:15 PM PDT 24
Peak memory 213632 kb
Host smart-d209638d-0b8e-43ed-8e48-7e43e2de098e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262680396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
262680396
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.376423907
Short name T81
Test name
Test status
Simulation time 3393054321 ps
CPU time 6.77 seconds
Started Jun 23 06:15:09 PM PDT 24
Finished Jun 23 06:15:16 PM PDT 24
Peak memory 219848 kb
Host smart-e10e12d2-3f2a-4d2e-a5fd-1ad881c011b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376423907 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.376423907
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.336827117
Short name T377
Test name
Test status
Simulation time 91042591 ps
CPU time 2.2 seconds
Started Jun 23 06:15:05 PM PDT 24
Finished Jun 23 06:15:08 PM PDT 24
Peak memory 213896 kb
Host smart-ec77dd6b-b280-476c-9dbb-cc9671fdf910
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336827117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.336827117
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.160936099
Short name T274
Test name
Test status
Simulation time 2510705189 ps
CPU time 7.71 seconds
Started Jun 23 06:15:00 PM PDT 24
Finished Jun 23 06:15:08 PM PDT 24
Peak memory 205492 kb
Host smart-e83b4675-8930-4a28-96e5-dbdf63ea1829
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160936099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
rv_dm_jtag_dmi_csr_bit_bash.160936099
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3732410576
Short name T308
Test name
Test status
Simulation time 3635321995 ps
CPU time 10.55 seconds
Started Jun 23 06:15:05 PM PDT 24
Finished Jun 23 06:15:15 PM PDT 24
Peak memory 205464 kb
Host smart-2517cdab-4a01-467c-aa3c-0ee2fea1a25a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732410576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3732410576
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2709143698
Short name T70
Test name
Test status
Simulation time 445337636 ps
CPU time 1.85 seconds
Started Jun 23 06:15:01 PM PDT 24
Finished Jun 23 06:15:04 PM PDT 24
Peak memory 205128 kb
Host smart-5658c2d3-9ed7-45f3-845f-56117ce32ab0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709143698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2709143698
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1587415228
Short name T126
Test name
Test status
Simulation time 861366017 ps
CPU time 7.9 seconds
Started Jun 23 06:15:05 PM PDT 24
Finished Jun 23 06:15:13 PM PDT 24
Peak memory 205500 kb
Host smart-bb88e8ef-a23a-4d97-bd1c-04bcdc38ec54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587415228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1587415228
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2808724285
Short name T73
Test name
Test status
Simulation time 555165668 ps
CPU time 2.39 seconds
Started Jun 23 06:15:05 PM PDT 24
Finished Jun 23 06:15:08 PM PDT 24
Peak memory 213660 kb
Host smart-111239ec-643b-4ea9-a043-3759f31198b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808724285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2808724285
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.282654833
Short name T394
Test name
Test status
Simulation time 2412763329 ps
CPU time 11.32 seconds
Started Jun 23 06:15:02 PM PDT 24
Finished Jun 23 06:15:13 PM PDT 24
Peak memory 213784 kb
Host smart-c8f5aa8d-3359-42a8-9db1-9efec129a8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282654833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.282654833
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2472589343
Short name T403
Test name
Test status
Simulation time 3214081641 ps
CPU time 8.48 seconds
Started Jun 23 06:15:08 PM PDT 24
Finished Jun 23 06:15:17 PM PDT 24
Peak memory 213820 kb
Host smart-4f21c192-890a-48b3-a428-d7a5552ab132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472589343 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2472589343
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1669926299
Short name T93
Test name
Test status
Simulation time 179233500 ps
CPU time 1.7 seconds
Started Jun 23 06:15:08 PM PDT 24
Finished Jun 23 06:15:10 PM PDT 24
Peak memory 213688 kb
Host smart-791a8a95-1964-4bb8-a4fd-b12e7faeabea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669926299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1669926299
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3942010923
Short name T415
Test name
Test status
Simulation time 6024806328 ps
CPU time 6.05 seconds
Started Jun 23 06:15:06 PM PDT 24
Finished Jun 23 06:15:12 PM PDT 24
Peak memory 205428 kb
Host smart-566db944-a046-4a2f-a7fc-04ffa3c59cf7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942010923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3942010923
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2283825205
Short name T299
Test name
Test status
Simulation time 2123402158 ps
CPU time 4.9 seconds
Started Jun 23 06:15:04 PM PDT 24
Finished Jun 23 06:15:10 PM PDT 24
Peak memory 205308 kb
Host smart-81a46713-3b3b-47c5-a8f1-ac0a60cf72a4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283825205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2283825205
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.630508158
Short name T407
Test name
Test status
Simulation time 1142218182 ps
CPU time 1.42 seconds
Started Jun 23 06:15:05 PM PDT 24
Finished Jun 23 06:15:07 PM PDT 24
Peak memory 205164 kb
Host smart-2cf6ba72-f874-4284-a808-7b4bcfe07d43
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630508158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.630508158
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2916602856
Short name T361
Test name
Test status
Simulation time 1067781260 ps
CPU time 4.43 seconds
Started Jun 23 06:15:08 PM PDT 24
Finished Jun 23 06:15:13 PM PDT 24
Peak memory 205476 kb
Host smart-02385d78-25ba-4263-9b08-a3e0d5ea9a3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916602856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2916602856
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.833045531
Short name T416
Test name
Test status
Simulation time 164385078 ps
CPU time 3 seconds
Started Jun 23 06:15:07 PM PDT 24
Finished Jun 23 06:15:10 PM PDT 24
Peak memory 213724 kb
Host smart-66e91155-b2c4-4bd9-97c4-e69e852a801b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833045531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.833045531
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1762620026
Short name T318
Test name
Test status
Simulation time 3730049294 ps
CPU time 5.16 seconds
Started Jun 23 06:15:14 PM PDT 24
Finished Jun 23 06:15:20 PM PDT 24
Peak memory 220000 kb
Host smart-de314392-5487-425d-bf3d-4858550dea5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762620026 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1762620026
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.163114146
Short name T125
Test name
Test status
Simulation time 100237731 ps
CPU time 2.4 seconds
Started Jun 23 06:15:12 PM PDT 24
Finished Jun 23 06:15:15 PM PDT 24
Peak memory 213700 kb
Host smart-062ab337-c232-41ec-9b88-00347572243b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163114146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.163114146
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2066995073
Short name T280
Test name
Test status
Simulation time 168316702 ps
CPU time 1.06 seconds
Started Jun 23 06:15:13 PM PDT 24
Finished Jun 23 06:15:14 PM PDT 24
Peak memory 205164 kb
Host smart-a47bcda8-5392-48ec-9e5d-64c4b6783a22
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066995073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2066995073
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4011488499
Short name T282
Test name
Test status
Simulation time 9773169513 ps
CPU time 25.15 seconds
Started Jun 23 06:15:07 PM PDT 24
Finished Jun 23 06:15:33 PM PDT 24
Peak memory 205512 kb
Host smart-6b5b3e34-8dca-4805-8427-a0d75fb19ed3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011488499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4011488499
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.463704346
Short name T330
Test name
Test status
Simulation time 318868078 ps
CPU time 1.44 seconds
Started Jun 23 06:15:08 PM PDT 24
Finished Jun 23 06:15:10 PM PDT 24
Peak memory 205160 kb
Host smart-1ad49f66-ce1b-491a-bb8a-cecf47036b68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463704346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.463704346
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1229480889
Short name T128
Test name
Test status
Simulation time 1433054245 ps
CPU time 4.66 seconds
Started Jun 23 06:15:13 PM PDT 24
Finished Jun 23 06:15:18 PM PDT 24
Peak memory 205484 kb
Host smart-aa8af339-6681-4c96-89b7-92645d3c5028
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229480889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1229480889
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3526308000
Short name T383
Test name
Test status
Simulation time 104837644 ps
CPU time 4.73 seconds
Started Jun 23 06:15:11 PM PDT 24
Finished Jun 23 06:15:16 PM PDT 24
Peak memory 214004 kb
Host smart-3a3d4b8b-dfa0-4a1e-9ff6-f962537b1181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526308000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3526308000
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1568750918
Short name T369
Test name
Test status
Simulation time 8731333416 ps
CPU time 9.72 seconds
Started Jun 23 06:15:15 PM PDT 24
Finished Jun 23 06:15:25 PM PDT 24
Peak memory 220916 kb
Host smart-1111fec3-b72a-4e76-b5d8-1d19874edc4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568750918 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1568750918
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2544288384
Short name T92
Test name
Test status
Simulation time 185951707 ps
CPU time 1.53 seconds
Started Jun 23 06:15:12 PM PDT 24
Finished Jun 23 06:15:14 PM PDT 24
Peak memory 213656 kb
Host smart-5c79ec80-ef58-4d25-9ba3-775a16873f76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544288384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2544288384
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.420978142
Short name T295
Test name
Test status
Simulation time 10766075108 ps
CPU time 9.56 seconds
Started Jun 23 06:15:11 PM PDT 24
Finished Jun 23 06:15:21 PM PDT 24
Peak memory 205460 kb
Host smart-27f7fbee-40e2-49fd-aa50-a49714c8f9c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420978142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.420978142
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2344877721
Short name T272
Test name
Test status
Simulation time 6743980120 ps
CPU time 8.83 seconds
Started Jun 23 06:15:12 PM PDT 24
Finished Jun 23 06:15:21 PM PDT 24
Peak memory 205540 kb
Host smart-6a3ac7cf-8a75-4a01-b9e6-ecc382da05f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344877721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2344877721
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2663982665
Short name T405
Test name
Test status
Simulation time 442496362 ps
CPU time 1.33 seconds
Started Jun 23 06:15:13 PM PDT 24
Finished Jun 23 06:15:15 PM PDT 24
Peak memory 205128 kb
Host smart-aaa6812c-7279-4ef8-a344-91ee0223a8ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663982665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2663982665
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1044918253
Short name T114
Test name
Test status
Simulation time 3438226160 ps
CPU time 4.26 seconds
Started Jun 23 06:15:12 PM PDT 24
Finished Jun 23 06:15:16 PM PDT 24
Peak memory 205612 kb
Host smart-32393a28-40bd-41a2-9026-fab8212d595c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044918253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1044918253
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.732066657
Short name T293
Test name
Test status
Simulation time 181909133 ps
CPU time 4.54 seconds
Started Jun 23 06:15:16 PM PDT 24
Finished Jun 23 06:15:21 PM PDT 24
Peak memory 213760 kb
Host smart-957cc2be-d416-4108-a6d3-718500dc5b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732066657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.732066657
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3724022009
Short name T61
Test name
Test status
Simulation time 6924106803 ps
CPU time 19.23 seconds
Started Jun 23 06:15:12 PM PDT 24
Finished Jun 23 06:15:31 PM PDT 24
Peak memory 213824 kb
Host smart-d46d9c22-1d9f-493a-a899-d6fa70889c47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724022009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
724022009
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1868260483
Short name T353
Test name
Test status
Simulation time 59336456 ps
CPU time 2.51 seconds
Started Jun 23 06:15:17 PM PDT 24
Finished Jun 23 06:15:20 PM PDT 24
Peak memory 221816 kb
Host smart-c9e02ab6-fd63-46a8-bdec-0eb883b000bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868260483 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1868260483
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2455344963
Short name T414
Test name
Test status
Simulation time 74043803 ps
CPU time 1.56 seconds
Started Jun 23 06:15:18 PM PDT 24
Finished Jun 23 06:15:20 PM PDT 24
Peak memory 213852 kb
Host smart-c2f86972-f858-4509-9fb5-dd24c45ddc91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455344963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2455344963
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2960728343
Short name T290
Test name
Test status
Simulation time 5807859480 ps
CPU time 3.44 seconds
Started Jun 23 06:15:19 PM PDT 24
Finished Jun 23 06:15:23 PM PDT 24
Peak memory 205548 kb
Host smart-26c33f9a-6c8f-4733-bfae-1facca05ec44
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960728343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2960728343
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3335311619
Short name T285
Test name
Test status
Simulation time 2982848312 ps
CPU time 2.87 seconds
Started Jun 23 06:15:13 PM PDT 24
Finished Jun 23 06:15:16 PM PDT 24
Peak memory 205464 kb
Host smart-6ac9c946-aae6-4696-a3fa-e6108cd69311
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335311619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3335311619
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.179867389
Short name T332
Test name
Test status
Simulation time 632314590 ps
CPU time 1.47 seconds
Started Jun 23 06:15:15 PM PDT 24
Finished Jun 23 06:15:17 PM PDT 24
Peak memory 205064 kb
Host smart-e27f97f5-e1a1-4f3a-8bb3-6b5de18e9152
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179867389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.179867389
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.218602541
Short name T329
Test name
Test status
Simulation time 1131999422 ps
CPU time 7.55 seconds
Started Jun 23 06:15:18 PM PDT 24
Finished Jun 23 06:15:26 PM PDT 24
Peak memory 205444 kb
Host smart-ab5586f1-7b83-4990-80dd-5fc30a7b7699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218602541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.218602541
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1510410048
Short name T370
Test name
Test status
Simulation time 1699008064 ps
CPU time 4.63 seconds
Started Jun 23 06:15:17 PM PDT 24
Finished Jun 23 06:15:22 PM PDT 24
Peak memory 213764 kb
Host smart-8ba4d85c-451a-40a5-b592-65abc3e4b8d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510410048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1510410048
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4181249896
Short name T134
Test name
Test status
Simulation time 2036026232 ps
CPU time 13.46 seconds
Started Jun 23 06:15:16 PM PDT 24
Finished Jun 23 06:15:30 PM PDT 24
Peak memory 213664 kb
Host smart-be6fc2ed-2f49-4def-994f-63151c9e946c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181249896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4
181249896
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2477769920
Short name T343
Test name
Test status
Simulation time 195870755 ps
CPU time 2.34 seconds
Started Jun 23 06:15:18 PM PDT 24
Finished Jun 23 06:15:21 PM PDT 24
Peak memory 218096 kb
Host smart-a4daa2ff-4271-4537-b1ba-575bfe107e1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477769920 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2477769920
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2262651708
Short name T340
Test name
Test status
Simulation time 82763630 ps
CPU time 2.21 seconds
Started Jun 23 06:15:16 PM PDT 24
Finished Jun 23 06:15:18 PM PDT 24
Peak memory 213628 kb
Host smart-56d86afd-dceb-43cd-8e27-875df01483fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262651708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2262651708
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1661338276
Short name T300
Test name
Test status
Simulation time 24344183291 ps
CPU time 16.89 seconds
Started Jun 23 06:15:17 PM PDT 24
Finished Jun 23 06:15:35 PM PDT 24
Peak memory 205372 kb
Host smart-5cd9f23b-2c48-454d-9948-d12b60ac6946
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661338276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.1661338276
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2493855323
Short name T384
Test name
Test status
Simulation time 7046158436 ps
CPU time 8.51 seconds
Started Jun 23 06:15:19 PM PDT 24
Finished Jun 23 06:15:28 PM PDT 24
Peak memory 205388 kb
Host smart-68c55964-fbe0-477b-b316-48031dd7dddd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493855323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2493855323
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3142574690
Short name T338
Test name
Test status
Simulation time 249914745 ps
CPU time 1.1 seconds
Started Jun 23 06:15:20 PM PDT 24
Finished Jun 23 06:15:21 PM PDT 24
Peak memory 205156 kb
Host smart-6f55ded3-e08c-425a-aa5a-d2d88a20fbc9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142574690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3142574690
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1179115191
Short name T91
Test name
Test status
Simulation time 242075645 ps
CPU time 6.4 seconds
Started Jun 23 06:15:17 PM PDT 24
Finished Jun 23 06:15:24 PM PDT 24
Peak memory 205504 kb
Host smart-d5c266f9-079b-4805-83a2-673b276f4bf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179115191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1179115191
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2892806655
Short name T345
Test name
Test status
Simulation time 1454417013 ps
CPU time 2.56 seconds
Started Jun 23 06:15:16 PM PDT 24
Finished Jun 23 06:15:19 PM PDT 24
Peak memory 213768 kb
Host smart-52c6d8a3-9b8a-45b2-9bc1-d6fb8e57e7dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892806655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2892806655
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3722913786
Short name T395
Test name
Test status
Simulation time 6843187143 ps
CPU time 11.34 seconds
Started Jun 23 06:15:17 PM PDT 24
Finished Jun 23 06:15:28 PM PDT 24
Peak memory 213824 kb
Host smart-b0383763-7791-4d69-8f2f-cf877536a932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722913786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
722913786
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1865401392
Short name T129
Test name
Test status
Simulation time 5657661930 ps
CPU time 30.16 seconds
Started Jun 23 06:14:08 PM PDT 24
Finished Jun 23 06:14:39 PM PDT 24
Peak memory 205496 kb
Host smart-97178f51-3c39-4408-83f5-287cf10a9b0c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865401392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1865401392
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1943471049
Short name T87
Test name
Test status
Simulation time 435139235 ps
CPU time 3.02 seconds
Started Jun 23 06:14:16 PM PDT 24
Finished Jun 23 06:14:19 PM PDT 24
Peak memory 213744 kb
Host smart-dfebcf1d-408e-48e1-bd40-dd394befc4eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943471049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1943471049
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3040417285
Short name T326
Test name
Test status
Simulation time 4349332698 ps
CPU time 3.91 seconds
Started Jun 23 06:14:15 PM PDT 24
Finished Jun 23 06:14:19 PM PDT 24
Peak memory 221904 kb
Host smart-d2b6cbdf-c4ca-4ff5-a5e3-94c1694addf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040417285 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3040417285
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2566726370
Short name T366
Test name
Test status
Simulation time 104861280 ps
CPU time 2.17 seconds
Started Jun 23 06:14:14 PM PDT 24
Finished Jun 23 06:14:17 PM PDT 24
Peak memory 213576 kb
Host smart-81bf44e6-1442-4dd6-a1f4-1f950b7f1b9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566726370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2566726370
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2929207418
Short name T358
Test name
Test status
Simulation time 33646520500 ps
CPU time 44.43 seconds
Started Jun 23 06:14:11 PM PDT 24
Finished Jun 23 06:14:55 PM PDT 24
Peak memory 205544 kb
Host smart-e04ac04e-36ee-494e-85ba-4341bf5d0ee9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929207418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2929207418
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1151846453
Short name T278
Test name
Test status
Simulation time 89754499 ps
CPU time 0.7 seconds
Started Jun 23 06:14:11 PM PDT 24
Finished Jun 23 06:14:12 PM PDT 24
Peak memory 205172 kb
Host smart-8b245e11-3305-490c-a26c-5222308e1888
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151846453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1151846453
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4216989507
Short name T101
Test name
Test status
Simulation time 7052656561 ps
CPU time 9.51 seconds
Started Jun 23 06:14:08 PM PDT 24
Finished Jun 23 06:14:18 PM PDT 24
Peak memory 205652 kb
Host smart-f91302cd-1275-4810-8d35-952c00836666
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216989507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.4216989507
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1462318217
Short name T388
Test name
Test status
Simulation time 2874275151 ps
CPU time 9.2 seconds
Started Jun 23 06:14:12 PM PDT 24
Finished Jun 23 06:14:22 PM PDT 24
Peak memory 205464 kb
Host smart-2329cb84-77af-4148-854a-2aa3459859cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462318217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
462318217
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2881582625
Short name T348
Test name
Test status
Simulation time 889819920 ps
CPU time 2.8 seconds
Started Jun 23 06:14:11 PM PDT 24
Finished Jun 23 06:14:14 PM PDT 24
Peak memory 205064 kb
Host smart-af2f5f55-b943-463e-bc59-4b89b4aa2139
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881582625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2881582625
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2808557965
Short name T307
Test name
Test status
Simulation time 25532052604 ps
CPU time 67.34 seconds
Started Jun 23 06:14:06 PM PDT 24
Finished Jun 23 06:15:14 PM PDT 24
Peak memory 205464 kb
Host smart-1d3fd83b-a047-4ecd-864e-29c02d987c2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808557965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2808557965
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4052630997
Short name T413
Test name
Test status
Simulation time 357043286 ps
CPU time 0.87 seconds
Started Jun 23 06:14:05 PM PDT 24
Finished Jun 23 06:14:06 PM PDT 24
Peak memory 205112 kb
Host smart-84bf9077-9068-47e0-9d22-f399cf0edf27
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052630997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.4052630997
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.137608838
Short name T390
Test name
Test status
Simulation time 249609660 ps
CPU time 1.28 seconds
Started Jun 23 06:14:05 PM PDT 24
Finished Jun 23 06:14:06 PM PDT 24
Peak memory 205152 kb
Host smart-a8f7c1b6-174a-445e-8239-8c266bcb1b55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137608838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.137608838
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2244504773
Short name T378
Test name
Test status
Simulation time 156769764 ps
CPU time 0.77 seconds
Started Jun 23 06:14:16 PM PDT 24
Finished Jun 23 06:14:18 PM PDT 24
Peak memory 205100 kb
Host smart-800681c2-8a91-4a1b-93af-6a437796efdc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244504773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2244504773
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3946127786
Short name T306
Test name
Test status
Simulation time 57994214 ps
CPU time 0.75 seconds
Started Jun 23 06:14:18 PM PDT 24
Finished Jun 23 06:14:20 PM PDT 24
Peak memory 205088 kb
Host smart-5af2a849-99a1-4c7c-84f3-1f06a09ff763
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946127786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3946127786
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4169857662
Short name T116
Test name
Test status
Simulation time 203041980 ps
CPU time 6.59 seconds
Started Jun 23 06:14:16 PM PDT 24
Finished Jun 23 06:14:23 PM PDT 24
Peak memory 205532 kb
Host smart-47510669-6527-4967-b60c-218ccc9384c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169857662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.4169857662
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2086739006
Short name T374
Test name
Test status
Simulation time 79348444153 ps
CPU time 73.95 seconds
Started Jun 23 06:14:12 PM PDT 24
Finished Jun 23 06:15:26 PM PDT 24
Peak memory 224756 kb
Host smart-98075582-8938-4794-b568-1e9bc5acd7f9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086739006 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2086739006
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3892540839
Short name T184
Test name
Test status
Simulation time 146939627 ps
CPU time 4.16 seconds
Started Jun 23 06:14:09 PM PDT 24
Finished Jun 23 06:14:14 PM PDT 24
Peak memory 213756 kb
Host smart-39316c0a-4176-43e6-a780-8dc94211faf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892540839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3892540839
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1953618946
Short name T375
Test name
Test status
Simulation time 727284527 ps
CPU time 8.81 seconds
Started Jun 23 06:14:10 PM PDT 24
Finished Jun 23 06:14:19 PM PDT 24
Peak memory 213636 kb
Host smart-5ccb4dd4-1311-405a-a5a1-19a66a085313
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953618946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1953618946
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1311641631
Short name T88
Test name
Test status
Simulation time 7184800416 ps
CPU time 75.21 seconds
Started Jun 23 06:14:18 PM PDT 24
Finished Jun 23 06:15:34 PM PDT 24
Peak memory 213808 kb
Host smart-6a5a0527-f9fa-48c7-9886-62bd79c40483
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311641631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1311641631
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3984446497
Short name T89
Test name
Test status
Simulation time 5094121852 ps
CPU time 32.56 seconds
Started Jun 23 06:14:25 PM PDT 24
Finished Jun 23 06:14:58 PM PDT 24
Peak memory 205624 kb
Host smart-181c84db-d0e8-4ca1-a9b8-9b70a8775cb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984446497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3984446497
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1312607492
Short name T120
Test name
Test status
Simulation time 519698734 ps
CPU time 2.49 seconds
Started Jun 23 06:14:22 PM PDT 24
Finished Jun 23 06:14:24 PM PDT 24
Peak memory 213724 kb
Host smart-4870348d-310b-49ec-be21-69e8bd487536
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312607492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1312607492
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.741971703
Short name T319
Test name
Test status
Simulation time 4450335883 ps
CPU time 4.51 seconds
Started Jun 23 06:14:29 PM PDT 24
Finished Jun 23 06:14:34 PM PDT 24
Peak memory 219072 kb
Host smart-c5968fe4-00ca-49eb-b91e-f2de1f2044ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741971703 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.741971703
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4164384416
Short name T118
Test name
Test status
Simulation time 519104344 ps
CPU time 2.58 seconds
Started Jun 23 06:14:24 PM PDT 24
Finished Jun 23 06:14:27 PM PDT 24
Peak memory 213680 kb
Host smart-cc435ad9-4d43-4f01-8230-6dc0b9ec430a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164384416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4164384416
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1080316451
Short name T310
Test name
Test status
Simulation time 152142976817 ps
CPU time 354.76 seconds
Started Jun 23 06:14:21 PM PDT 24
Finished Jun 23 06:20:16 PM PDT 24
Peak memory 206444 kb
Host smart-95496a4b-b92c-44b9-85ea-3c6c451cf476
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080316451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1080316451
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2825634456
Short name T355
Test name
Test status
Simulation time 29459129188 ps
CPU time 17.8 seconds
Started Jun 23 06:14:23 PM PDT 24
Finished Jun 23 06:14:42 PM PDT 24
Peak memory 205444 kb
Host smart-0d24d66f-5bd2-4974-89c5-e2b227e953b3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825634456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2825634456
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2240768707
Short name T104
Test name
Test status
Simulation time 9260809464 ps
CPU time 27.36 seconds
Started Jun 23 06:14:24 PM PDT 24
Finished Jun 23 06:14:52 PM PDT 24
Peak memory 205624 kb
Host smart-45f067a6-e666-4e9c-ba04-b6845a7d350d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240768707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2240768707
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.801853558
Short name T270
Test name
Test status
Simulation time 5774570149 ps
CPU time 5.36 seconds
Started Jun 23 06:14:23 PM PDT 24
Finished Jun 23 06:14:29 PM PDT 24
Peak memory 205472 kb
Host smart-71709216-097a-4915-b123-f9d94125cf3e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801853558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.801853558
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4004724638
Short name T341
Test name
Test status
Simulation time 483079164 ps
CPU time 1.38 seconds
Started Jun 23 06:14:24 PM PDT 24
Finished Jun 23 06:14:25 PM PDT 24
Peak memory 205172 kb
Host smart-57223af2-cfff-40a3-97c4-89ba8724e7ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004724638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4004724638
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3957174132
Short name T382
Test name
Test status
Simulation time 6477166420 ps
CPU time 7.22 seconds
Started Jun 23 06:14:23 PM PDT 24
Finished Jun 23 06:14:31 PM PDT 24
Peak memory 205440 kb
Host smart-84122a93-2472-4930-b304-87b250f46392
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957174132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3957174132
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.614135867
Short name T349
Test name
Test status
Simulation time 546614720 ps
CPU time 1.94 seconds
Started Jun 23 06:14:23 PM PDT 24
Finished Jun 23 06:14:25 PM PDT 24
Peak memory 205228 kb
Host smart-ac27d39f-8c06-4c6e-8be6-00b680c9fb2f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614135867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.614135867
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2251605399
Short name T401
Test name
Test status
Simulation time 649932500 ps
CPU time 2.36 seconds
Started Jun 23 06:14:21 PM PDT 24
Finished Jun 23 06:14:24 PM PDT 24
Peak memory 205164 kb
Host smart-0009d5b0-8e26-4ea7-94e3-608c79b0ae55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251605399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
251605399
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2632984155
Short name T328
Test name
Test status
Simulation time 127529117 ps
CPU time 0.74 seconds
Started Jun 23 06:14:20 PM PDT 24
Finished Jun 23 06:14:21 PM PDT 24
Peak memory 205112 kb
Host smart-88000941-d8c6-4c7c-8b7d-7fcf04251f9e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632984155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2632984155
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4119868057
Short name T279
Test name
Test status
Simulation time 143273409 ps
CPU time 1.01 seconds
Started Jun 23 06:14:22 PM PDT 24
Finished Jun 23 06:14:23 PM PDT 24
Peak memory 205132 kb
Host smart-4a3e2df5-4615-43bb-aade-f8363afa1155
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119868057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.4119868057
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1893690227
Short name T105
Test name
Test status
Simulation time 345111631 ps
CPU time 3.69 seconds
Started Jun 23 06:14:30 PM PDT 24
Finished Jun 23 06:14:35 PM PDT 24
Peak memory 205552 kb
Host smart-097cefc9-4abb-4a01-bcdf-d9f8c261c2b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893690227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1893690227
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2416324514
Short name T98
Test name
Test status
Simulation time 167375869 ps
CPU time 2.36 seconds
Started Jun 23 06:14:22 PM PDT 24
Finished Jun 23 06:14:25 PM PDT 24
Peak memory 213796 kb
Host smart-38c3eb6f-0d14-4151-8732-d95e2cab7c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416324514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2416324514
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2239432202
Short name T408
Test name
Test status
Simulation time 5299765079 ps
CPU time 29.41 seconds
Started Jun 23 06:14:21 PM PDT 24
Finished Jun 23 06:14:51 PM PDT 24
Peak memory 221204 kb
Host smart-b4bf7cfb-cc45-48f9-b14e-42308602eccc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239432202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2239432202
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1400201780
Short name T317
Test name
Test status
Simulation time 23449229866 ps
CPU time 33.24 seconds
Started Jun 23 06:14:26 PM PDT 24
Finished Jun 23 06:14:59 PM PDT 24
Peak memory 205672 kb
Host smart-be425f8a-aa9a-40ed-abc3-1a1ef482638b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400201780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1400201780
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.766785203
Short name T124
Test name
Test status
Simulation time 14730344447 ps
CPU time 41.27 seconds
Started Jun 23 06:14:30 PM PDT 24
Finished Jun 23 06:15:12 PM PDT 24
Peak memory 205804 kb
Host smart-b01e99a4-b79d-4fb6-b167-77f73273aff7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766785203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.766785203
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1435106530
Short name T110
Test name
Test status
Simulation time 83761238 ps
CPU time 1.7 seconds
Started Jun 23 06:14:32 PM PDT 24
Finished Jun 23 06:14:34 PM PDT 24
Peak memory 213736 kb
Host smart-83688af8-e577-4227-ab62-1b4c233752dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435106530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1435106530
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2792327823
Short name T301
Test name
Test status
Simulation time 3135992776 ps
CPU time 3.34 seconds
Started Jun 23 06:14:36 PM PDT 24
Finished Jun 23 06:14:39 PM PDT 24
Peak memory 222032 kb
Host smart-e82bdb61-1cfd-4aea-8ac2-d632d1cca33e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792327823 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2792327823
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.162135404
Short name T119
Test name
Test status
Simulation time 115272242 ps
CPU time 2.24 seconds
Started Jun 23 06:14:33 PM PDT 24
Finished Jun 23 06:14:35 PM PDT 24
Peak memory 213724 kb
Host smart-aba80231-25ea-494c-9f15-c1a6be0000be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162135404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.162135404
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2732698569
Short name T275
Test name
Test status
Simulation time 234060474857 ps
CPU time 609.28 seconds
Started Jun 23 06:14:31 PM PDT 24
Finished Jun 23 06:24:41 PM PDT 24
Peak memory 211908 kb
Host smart-596d0a46-128e-437a-8a1e-580273de8d27
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732698569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2732698569
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.586138983
Short name T327
Test name
Test status
Simulation time 18461043197 ps
CPU time 12.49 seconds
Started Jun 23 06:14:30 PM PDT 24
Finished Jun 23 06:14:42 PM PDT 24
Peak memory 205504 kb
Host smart-5f02e6d8-c244-46f9-aba4-0adab2efdce0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586138983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.586138983
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4130726402
Short name T102
Test name
Test status
Simulation time 2244217312 ps
CPU time 7.19 seconds
Started Jun 23 06:14:31 PM PDT 24
Finished Jun 23 06:14:38 PM PDT 24
Peak memory 205620 kb
Host smart-c0c772fb-73fe-4728-8cf6-f14265f16421
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130726402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.4130726402
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2673300928
Short name T286
Test name
Test status
Simulation time 4985355055 ps
CPU time 9.86 seconds
Started Jun 23 06:14:33 PM PDT 24
Finished Jun 23 06:14:43 PM PDT 24
Peak memory 205472 kb
Host smart-c1dc95a8-bdfb-4ff3-87b8-66b030261ea6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673300928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
673300928
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4255861359
Short name T69
Test name
Test status
Simulation time 291639603 ps
CPU time 1.4 seconds
Started Jun 23 06:14:27 PM PDT 24
Finished Jun 23 06:14:29 PM PDT 24
Peak memory 205120 kb
Host smart-3e4b14ca-6f7d-4226-80ce-e3c65c648a0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255861359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.4255861359
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2114491733
Short name T305
Test name
Test status
Simulation time 13900019297 ps
CPU time 32.74 seconds
Started Jun 23 06:14:28 PM PDT 24
Finished Jun 23 06:15:02 PM PDT 24
Peak memory 205472 kb
Host smart-87ade7c7-1b60-40f1-86b8-45899e84833a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114491733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2114491733
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4063846378
Short name T288
Test name
Test status
Simulation time 285928586 ps
CPU time 0.88 seconds
Started Jun 23 06:14:29 PM PDT 24
Finished Jun 23 06:14:30 PM PDT 24
Peak memory 205220 kb
Host smart-b8a119ea-000c-45cc-b578-d0359c67e90e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063846378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.4063846378
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.351352398
Short name T291
Test name
Test status
Simulation time 733706711 ps
CPU time 1.15 seconds
Started Jun 23 06:14:27 PM PDT 24
Finished Jun 23 06:14:28 PM PDT 24
Peak memory 205120 kb
Host smart-9d55d2a8-a6d6-472f-a7f1-4b6dd08fcac2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351352398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.351352398
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.662562788
Short name T400
Test name
Test status
Simulation time 88749704 ps
CPU time 0.73 seconds
Started Jun 23 06:14:32 PM PDT 24
Finished Jun 23 06:14:33 PM PDT 24
Peak memory 205292 kb
Host smart-eb2f47ee-b901-4daa-87f0-6852f81cc71e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662562788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.662562788
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2023088323
Short name T324
Test name
Test status
Simulation time 68728786 ps
CPU time 0.72 seconds
Started Jun 23 06:14:32 PM PDT 24
Finished Jun 23 06:14:33 PM PDT 24
Peak memory 205172 kb
Host smart-399ea755-4525-48f5-80e7-4d738e3cef4f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023088323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2023088323
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.312685018
Short name T86
Test name
Test status
Simulation time 177238058 ps
CPU time 3.59 seconds
Started Jun 23 06:14:38 PM PDT 24
Finished Jun 23 06:14:42 PM PDT 24
Peak memory 205504 kb
Host smart-d7de8eb2-9b20-43cb-8068-e689399817a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312685018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.312685018
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2451823356
Short name T367
Test name
Test status
Simulation time 39016544412 ps
CPU time 108.95 seconds
Started Jun 23 06:14:32 PM PDT 24
Finished Jun 23 06:16:21 PM PDT 24
Peak memory 222100 kb
Host smart-b4e63970-b4ef-480b-b49d-61933f8226c3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451823356 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2451823356
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2859725111
Short name T357
Test name
Test status
Simulation time 1006450543 ps
CPU time 5.41 seconds
Started Jun 23 06:14:32 PM PDT 24
Finished Jun 23 06:14:38 PM PDT 24
Peak memory 213764 kb
Host smart-0b39a601-d1a0-4348-89d4-328256aba68f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859725111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2859725111
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.683109153
Short name T337
Test name
Test status
Simulation time 2024862110 ps
CPU time 9.94 seconds
Started Jun 23 06:14:32 PM PDT 24
Finished Jun 23 06:14:43 PM PDT 24
Peak memory 213700 kb
Host smart-722b438c-17c8-4055-864f-3430832d014f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683109153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.683109153
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2191698873
Short name T315
Test name
Test status
Simulation time 2032104602 ps
CPU time 5.15 seconds
Started Jun 23 06:14:43 PM PDT 24
Finished Jun 23 06:14:48 PM PDT 24
Peak memory 219780 kb
Host smart-7378ad76-6e3b-4c77-b23f-bc84083609cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191698873 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2191698873
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.543800258
Short name T111
Test name
Test status
Simulation time 493652120 ps
CPU time 2.63 seconds
Started Jun 23 06:14:40 PM PDT 24
Finished Jun 23 06:14:43 PM PDT 24
Peak memory 213660 kb
Host smart-a4abd626-e9dc-49af-955a-9555b87521cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543800258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.543800258
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.633454421
Short name T269
Test name
Test status
Simulation time 8659712824 ps
CPU time 7.21 seconds
Started Jun 23 06:14:39 PM PDT 24
Finished Jun 23 06:14:47 PM PDT 24
Peak memory 205496 kb
Host smart-2ad88e14-a404-49d7-9e5d-38f1a4c3660e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633454421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
v_dm_jtag_dmi_csr_bit_bash.633454421
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1137031088
Short name T283
Test name
Test status
Simulation time 1334019657 ps
CPU time 2.8 seconds
Started Jun 23 06:14:39 PM PDT 24
Finished Jun 23 06:14:42 PM PDT 24
Peak memory 205376 kb
Host smart-5f407587-6575-4268-a9e3-00ab9e0831ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137031088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
137031088
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2704151210
Short name T352
Test name
Test status
Simulation time 243472139 ps
CPU time 0.91 seconds
Started Jun 23 06:14:36 PM PDT 24
Finished Jun 23 06:14:37 PM PDT 24
Peak memory 205116 kb
Host smart-c5f25d44-ffde-4292-ba12-13e069c31acb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704151210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
704151210
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.145459493
Short name T109
Test name
Test status
Simulation time 1057473989 ps
CPU time 4.25 seconds
Started Jun 23 06:14:36 PM PDT 24
Finished Jun 23 06:14:41 PM PDT 24
Peak memory 205432 kb
Host smart-903fbf65-c78c-407b-a99a-05b1f8e75c50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145459493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.145459493
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3842466005
Short name T144
Test name
Test status
Simulation time 47114695339 ps
CPU time 22.67 seconds
Started Jun 23 06:14:37 PM PDT 24
Finished Jun 23 06:15:00 PM PDT 24
Peak memory 219124 kb
Host smart-45fc31de-a8a7-4241-8738-086a47f3cc6d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842466005 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3842466005
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1118641297
Short name T138
Test name
Test status
Simulation time 1404980628 ps
CPU time 8.51 seconds
Started Jun 23 06:14:39 PM PDT 24
Finished Jun 23 06:14:47 PM PDT 24
Peak memory 213632 kb
Host smart-af4ec906-f9c8-4fbb-a3ad-c1ee64540bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118641297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1118641297
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2573837891
Short name T397
Test name
Test status
Simulation time 237428906 ps
CPU time 3.95 seconds
Started Jun 23 06:14:45 PM PDT 24
Finished Jun 23 06:14:49 PM PDT 24
Peak memory 222040 kb
Host smart-f4437aeb-0153-4cc7-b166-166fde529814
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573837891 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2573837891
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.878649038
Short name T402
Test name
Test status
Simulation time 169834164 ps
CPU time 2.72 seconds
Started Jun 23 06:14:42 PM PDT 24
Finished Jun 23 06:14:45 PM PDT 24
Peak memory 213712 kb
Host smart-2e5e63d7-1205-4cac-9e9a-4460e734e7f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878649038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.878649038
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2403614026
Short name T276
Test name
Test status
Simulation time 33347383620 ps
CPU time 90.98 seconds
Started Jun 23 06:14:40 PM PDT 24
Finished Jun 23 06:16:12 PM PDT 24
Peak memory 205368 kb
Host smart-0ce17328-3b6f-4a24-a3c7-35af25690876
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403614026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2403614026
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3613057316
Short name T404
Test name
Test status
Simulation time 1430082772 ps
CPU time 2.7 seconds
Started Jun 23 06:14:44 PM PDT 24
Finished Jun 23 06:14:47 PM PDT 24
Peak memory 205504 kb
Host smart-9d73973e-1ee8-451d-86ab-8dd74a12832c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613057316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
613057316
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4172041377
Short name T71
Test name
Test status
Simulation time 197812033 ps
CPU time 0.92 seconds
Started Jun 23 06:14:43 PM PDT 24
Finished Jun 23 06:14:45 PM PDT 24
Peak memory 205120 kb
Host smart-d55a5124-2c95-4641-8ec0-c4df0f60096b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172041377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4
172041377
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2796421978
Short name T333
Test name
Test status
Simulation time 2650592643 ps
CPU time 6.78 seconds
Started Jun 23 06:14:42 PM PDT 24
Finished Jun 23 06:14:49 PM PDT 24
Peak memory 205552 kb
Host smart-35d27877-0741-4dd3-9791-eb8400a0676c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796421978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2796421978
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1040716711
Short name T56
Test name
Test status
Simulation time 55908267210 ps
CPU time 92.38 seconds
Started Jun 23 06:14:40 PM PDT 24
Finished Jun 23 06:16:13 PM PDT 24
Peak memory 222260 kb
Host smart-54d59645-ea22-47e3-a032-5ca8a358c84a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040716711 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1040716711
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1243904111
Short name T371
Test name
Test status
Simulation time 144946224 ps
CPU time 2.73 seconds
Started Jun 23 06:14:40 PM PDT 24
Finished Jun 23 06:14:43 PM PDT 24
Peak memory 213800 kb
Host smart-85d63fb1-f28a-4bbf-bf90-196c39f8b433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243904111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1243904111
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1366877801
Short name T339
Test name
Test status
Simulation time 3258521844 ps
CPU time 11.85 seconds
Started Jun 23 06:14:44 PM PDT 24
Finished Jun 23 06:14:56 PM PDT 24
Peak memory 213800 kb
Host smart-ee5b71c8-b347-4dea-90b1-f3fd078b56ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366877801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1366877801
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2255456299
Short name T72
Test name
Test status
Simulation time 2156683258 ps
CPU time 7.21 seconds
Started Jun 23 06:14:51 PM PDT 24
Finished Jun 23 06:14:59 PM PDT 24
Peak memory 222112 kb
Host smart-ccbee147-a183-4023-a8f0-c9cfaa496354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255456299 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2255456299
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.996828120
Short name T123
Test name
Test status
Simulation time 148786719 ps
CPU time 2.26 seconds
Started Jun 23 06:14:49 PM PDT 24
Finished Jun 23 06:14:52 PM PDT 24
Peak memory 213680 kb
Host smart-49eafb1a-c9af-4c71-b211-33118993ceee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996828120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.996828120
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.488117680
Short name T322
Test name
Test status
Simulation time 30825499618 ps
CPU time 44.44 seconds
Started Jun 23 06:14:50 PM PDT 24
Finished Jun 23 06:15:35 PM PDT 24
Peak memory 205396 kb
Host smart-d5f7d015-1ed4-4ac1-a081-6ffd0567d2f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488117680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r
v_dm_jtag_dmi_csr_bit_bash.488117680
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1508452706
Short name T412
Test name
Test status
Simulation time 2559618352 ps
CPU time 4.8 seconds
Started Jun 23 06:14:50 PM PDT 24
Finished Jun 23 06:14:56 PM PDT 24
Peak memory 205388 kb
Host smart-3b6be361-ca89-4ec1-9b68-8568017ad16a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508452706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
508452706
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1246651344
Short name T321
Test name
Test status
Simulation time 277314560 ps
CPU time 0.77 seconds
Started Jun 23 06:14:47 PM PDT 24
Finished Jun 23 06:14:48 PM PDT 24
Peak memory 205172 kb
Host smart-66c0e890-5569-4ddb-a498-1bfaca1a9dd6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246651344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
246651344
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1134436115
Short name T346
Test name
Test status
Simulation time 81415704935 ps
CPU time 56.04 seconds
Started Jun 23 06:14:48 PM PDT 24
Finished Jun 23 06:15:45 PM PDT 24
Peak memory 230528 kb
Host smart-fa1953ce-9002-408f-b77d-78aa845e3b1c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134436115 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1134436115
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3755917114
Short name T311
Test name
Test status
Simulation time 203271728 ps
CPU time 4.66 seconds
Started Jun 23 06:14:52 PM PDT 24
Finished Jun 23 06:14:57 PM PDT 24
Peak memory 213108 kb
Host smart-fb6b3f17-8e46-4eca-9ab4-293b0f5040e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755917114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3755917114
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2267601356
Short name T136
Test name
Test status
Simulation time 946168083 ps
CPU time 9.84 seconds
Started Jun 23 06:14:47 PM PDT 24
Finished Jun 23 06:14:58 PM PDT 24
Peak memory 213704 kb
Host smart-5142d360-ba01-4290-a478-fe4eeb7ad9eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267601356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2267601356
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1121269082
Short name T364
Test name
Test status
Simulation time 150856257 ps
CPU time 2.81 seconds
Started Jun 23 06:15:01 PM PDT 24
Finished Jun 23 06:15:04 PM PDT 24
Peak memory 219680 kb
Host smart-3c728c24-f170-4145-9bde-e0372ca8668a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121269082 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1121269082
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2614365828
Short name T121
Test name
Test status
Simulation time 62513610 ps
CPU time 2.24 seconds
Started Jun 23 06:14:58 PM PDT 24
Finished Jun 23 06:15:01 PM PDT 24
Peak memory 213712 kb
Host smart-d09d39aa-4a06-4496-a206-bed3919adbec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614365828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2614365828
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1666356129
Short name T381
Test name
Test status
Simulation time 62643348 ps
CPU time 0.74 seconds
Started Jun 23 06:14:52 PM PDT 24
Finished Jun 23 06:14:53 PM PDT 24
Peak memory 204412 kb
Host smart-4ef73f59-9fa6-4b91-a7c4-2ad0b28dc6ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666356129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1666356129
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1659521237
Short name T284
Test name
Test status
Simulation time 1048285839 ps
CPU time 3.44 seconds
Started Jun 23 06:14:47 PM PDT 24
Finished Jun 23 06:14:51 PM PDT 24
Peak memory 205336 kb
Host smart-ecb388a5-f1bc-422b-8d98-9f5920f0faae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659521237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
659521237
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2934838456
Short name T362
Test name
Test status
Simulation time 431829397 ps
CPU time 1.24 seconds
Started Jun 23 06:14:50 PM PDT 24
Finished Jun 23 06:14:51 PM PDT 24
Peak memory 205160 kb
Host smart-ed05cec8-c867-42fd-a678-e48d6d310c83
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934838456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
934838456
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4214203012
Short name T108
Test name
Test status
Simulation time 322103553 ps
CPU time 4.18 seconds
Started Jun 23 06:14:54 PM PDT 24
Finished Jun 23 06:14:59 PM PDT 24
Peak memory 205476 kb
Host smart-045b618e-571d-46b8-8eec-63df45d6a245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214203012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.4214203012
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3759864702
Short name T372
Test name
Test status
Simulation time 50089477613 ps
CPU time 132.1 seconds
Started Jun 23 06:14:50 PM PDT 24
Finished Jun 23 06:17:02 PM PDT 24
Peak memory 222040 kb
Host smart-df181634-3eb0-441b-af4b-3a7ccff9527b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759864702 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3759864702
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3205629336
Short name T385
Test name
Test status
Simulation time 184395686 ps
CPU time 1.9 seconds
Started Jun 23 06:14:48 PM PDT 24
Finished Jun 23 06:14:50 PM PDT 24
Peak memory 213760 kb
Host smart-b6df8578-5435-4d69-97e8-97972ca7fad5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205629336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3205629336
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3524778778
Short name T140
Test name
Test status
Simulation time 1887028218 ps
CPU time 9.03 seconds
Started Jun 23 06:14:52 PM PDT 24
Finished Jun 23 06:15:01 PM PDT 24
Peak memory 213660 kb
Host smart-b4ba3ce2-251a-4ac6-8149-7ba3a2231be1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524778778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3524778778
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1508925151
Short name T303
Test name
Test status
Simulation time 609407968 ps
CPU time 3.52 seconds
Started Jun 23 06:14:54 PM PDT 24
Finished Jun 23 06:14:58 PM PDT 24
Peak memory 221928 kb
Host smart-3cd3f343-5d83-40d8-84e1-896162caf775
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508925151 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1508925151
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3772921328
Short name T302
Test name
Test status
Simulation time 79293896 ps
CPU time 1.57 seconds
Started Jun 23 06:14:50 PM PDT 24
Finished Jun 23 06:14:52 PM PDT 24
Peak memory 213692 kb
Host smart-b3b58a5a-5472-4138-bb1a-7f99acdc7847
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772921328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3772921328
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1953180478
Short name T304
Test name
Test status
Simulation time 14193897354 ps
CPU time 12.89 seconds
Started Jun 23 06:14:52 PM PDT 24
Finished Jun 23 06:15:05 PM PDT 24
Peak memory 205464 kb
Host smart-dd0e0906-c8cd-4f7d-b4fc-970992a6f154
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953180478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.1953180478
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.378856717
Short name T312
Test name
Test status
Simulation time 2355466904 ps
CPU time 2.46 seconds
Started Jun 23 06:14:53 PM PDT 24
Finished Jun 23 06:14:56 PM PDT 24
Peak memory 205492 kb
Host smart-34cba5a6-073f-4af2-bc59-3570ecdb0867
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378856717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.378856717
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2064676175
Short name T387
Test name
Test status
Simulation time 1185479864 ps
CPU time 1.29 seconds
Started Jun 23 06:14:53 PM PDT 24
Finished Jun 23 06:14:54 PM PDT 24
Peak memory 205124 kb
Host smart-47d3796b-e4d6-4589-896b-ef1907638964
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064676175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
064676175
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4086441653
Short name T347
Test name
Test status
Simulation time 1242525298 ps
CPU time 7.76 seconds
Started Jun 23 06:14:55 PM PDT 24
Finished Jun 23 06:15:04 PM PDT 24
Peak memory 205476 kb
Host smart-91a9a010-1ffa-4084-beed-31d4de6df16b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086441653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.4086441653
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.325091713
Short name T55
Test name
Test status
Simulation time 20452040373 ps
CPU time 26.47 seconds
Started Jun 23 06:14:53 PM PDT 24
Finished Jun 23 06:15:20 PM PDT 24
Peak memory 221992 kb
Host smart-09370e03-4585-40f9-8c4d-c569e37983f5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325091713 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.325091713
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.461816190
Short name T380
Test name
Test status
Simulation time 2297770070 ps
CPU time 3.8 seconds
Started Jun 23 06:14:51 PM PDT 24
Finished Jun 23 06:14:56 PM PDT 24
Peak memory 213944 kb
Host smart-f099705c-3891-4e12-9ad3-84d03526ad9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461816190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.461816190
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.809460355
Short name T75
Test name
Test status
Simulation time 984868795 ps
CPU time 11.3 seconds
Started Jun 23 06:15:00 PM PDT 24
Finished Jun 23 06:15:12 PM PDT 24
Peak memory 213768 kb
Host smart-9fa8d50b-51ca-4d4c-999e-564c7435601e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809460355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.809460355
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3271344127
Short name T165
Test name
Test status
Simulation time 66961436 ps
CPU time 0.82 seconds
Started Jun 23 06:00:18 PM PDT 24
Finished Jun 23 06:00:19 PM PDT 24
Peak memory 204808 kb
Host smart-2ceaaeab-7df5-4750-949b-85fa2618bedd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271344127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3271344127
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.4042201716
Short name T133
Test name
Test status
Simulation time 28584837994 ps
CPU time 16.33 seconds
Started Jun 23 06:00:00 PM PDT 24
Finished Jun 23 06:00:17 PM PDT 24
Peak memory 213356 kb
Host smart-3186f9ef-47e7-4ce4-ba14-2bbc3d0d4e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042201716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.4042201716
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.316092555
Short name T210
Test name
Test status
Simulation time 3034822764 ps
CPU time 9.51 seconds
Started Jun 23 05:59:58 PM PDT 24
Finished Jun 23 06:00:08 PM PDT 24
Peak memory 205308 kb
Host smart-fb081fd1-253a-4808-8315-c8f895accd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316092555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.316092555
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.211569486
Short name T11
Test name
Test status
Simulation time 8626381825 ps
CPU time 13.43 seconds
Started Jun 23 06:00:01 PM PDT 24
Finished Jun 23 06:00:15 PM PDT 24
Peak memory 205016 kb
Host smart-989ba98e-ae77-446b-b21f-ad1cf2c4dcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211569486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.211569486
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1882548390
Short name T148
Test name
Test status
Simulation time 3656593541 ps
CPU time 3.82 seconds
Started Jun 23 06:00:04 PM PDT 24
Finished Jun 23 06:00:08 PM PDT 24
Peak memory 205028 kb
Host smart-717a5fbb-4e93-4be3-a8fe-070290953ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882548390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1882548390
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.909104384
Short name T28
Test name
Test status
Simulation time 164919437 ps
CPU time 0.79 seconds
Started Jun 23 06:00:08 PM PDT 24
Finished Jun 23 06:00:10 PM PDT 24
Peak memory 204756 kb
Host smart-1cdb5a8d-2e7f-4f0a-a1fd-934b669b3a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909104384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.909104384
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2184225924
Short name T188
Test name
Test status
Simulation time 3497035762 ps
CPU time 3.99 seconds
Started Jun 23 05:59:59 PM PDT 24
Finished Jun 23 06:00:03 PM PDT 24
Peak memory 205136 kb
Host smart-db5ab38b-7cf6-43c5-8ce3-2b0984e123e4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184225924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2184225924
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1404782121
Short name T17
Test name
Test status
Simulation time 1174207364 ps
CPU time 2.07 seconds
Started Jun 23 06:00:06 PM PDT 24
Finished Jun 23 06:00:08 PM PDT 24
Peak memory 204904 kb
Host smart-ab8b0d98-ce93-4fe7-87a8-c9e75af0a378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404782121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1404782121
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1925248081
Short name T250
Test name
Test status
Simulation time 143600760 ps
CPU time 0.85 seconds
Started Jun 23 06:00:00 PM PDT 24
Finished Jun 23 06:00:01 PM PDT 24
Peak memory 204604 kb
Host smart-83422893-c9c1-489b-96c5-5cbdb5697857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925248081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1925248081
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4020383569
Short name T19
Test name
Test status
Simulation time 600706072 ps
CPU time 0.92 seconds
Started Jun 23 06:00:13 PM PDT 24
Finished Jun 23 06:00:14 PM PDT 24
Peak memory 204572 kb
Host smart-5a644a8e-1332-4f86-8178-e9f8f7ff3ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020383569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4020383569
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2286534780
Short name T190
Test name
Test status
Simulation time 2177939923 ps
CPU time 2.74 seconds
Started Jun 23 06:00:06 PM PDT 24
Finished Jun 23 06:00:09 PM PDT 24
Peak memory 204672 kb
Host smart-689bcd8a-1656-41b0-b1a7-8de1e483a48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286534780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2286534780
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2849967030
Short name T237
Test name
Test status
Simulation time 276416010 ps
CPU time 1.21 seconds
Started Jun 23 06:00:12 PM PDT 24
Finished Jun 23 06:00:14 PM PDT 24
Peak memory 204564 kb
Host smart-ab0e411c-7601-4f8b-9d8c-3170d2c52db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849967030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2849967030
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.233837848
Short name T202
Test name
Test status
Simulation time 643557329 ps
CPU time 1.08 seconds
Started Jun 23 06:00:07 PM PDT 24
Finished Jun 23 06:00:08 PM PDT 24
Peak memory 204616 kb
Host smart-efcf28f8-e837-4ac3-b4b1-50de8846ad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233837848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.233837848
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.837300361
Short name T153
Test name
Test status
Simulation time 360356287 ps
CPU time 0.83 seconds
Started Jun 23 06:00:02 PM PDT 24
Finished Jun 23 06:00:03 PM PDT 24
Peak memory 204700 kb
Host smart-73e0522f-c638-431b-83e5-f3ce9974cd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837300361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.837300361
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3337427779
Short name T2
Test name
Test status
Simulation time 1229636073 ps
CPU time 2.35 seconds
Started Jun 23 06:00:04 PM PDT 24
Finished Jun 23 06:00:07 PM PDT 24
Peak memory 204884 kb
Host smart-7f8ee5f3-4c4f-47c1-bb1f-adca3453d394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337427779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3337427779
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.60842963
Short name T21
Test name
Test status
Simulation time 5093581885 ps
CPU time 4.5 seconds
Started Jun 23 06:00:06 PM PDT 24
Finished Jun 23 06:00:11 PM PDT 24
Peak memory 205156 kb
Host smart-125e3f8b-129e-4dc9-8b5e-886838cffa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60842963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.60842963
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1607386432
Short name T100
Test name
Test status
Simulation time 2219910047 ps
CPU time 1.8 seconds
Started Jun 23 05:59:58 PM PDT 24
Finished Jun 23 06:00:00 PM PDT 24
Peak memory 205292 kb
Host smart-b2308e3c-4ac1-43ca-b2d9-14a8f2305176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607386432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1607386432
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2331806415
Short name T53
Test name
Test status
Simulation time 475074978 ps
CPU time 2.06 seconds
Started Jun 23 06:00:19 PM PDT 24
Finished Jun 23 06:00:21 PM PDT 24
Peak memory 228312 kb
Host smart-433ad959-a95b-4a18-af3c-bd70b33dac5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331806415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2331806415
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3411861129
Short name T224
Test name
Test status
Simulation time 1559149295 ps
CPU time 2.93 seconds
Started Jun 23 05:59:58 PM PDT 24
Finished Jun 23 06:00:01 PM PDT 24
Peak memory 204804 kb
Host smart-fedcef59-1032-4d07-865c-ae6a527ba046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411861129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3411861129
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.2509450969
Short name T49
Test name
Test status
Simulation time 138276283 ps
CPU time 1.09 seconds
Started Jun 23 06:00:27 PM PDT 24
Finished Jun 23 06:00:29 PM PDT 24
Peak memory 204712 kb
Host smart-eacdf592-13d9-4ee9-961b-694090dc1f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509450969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2509450969
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1788427053
Short name T203
Test name
Test status
Simulation time 52093722970 ps
CPU time 40.8 seconds
Started Jun 23 06:00:21 PM PDT 24
Finished Jun 23 06:01:02 PM PDT 24
Peak memory 213408 kb
Host smart-2576020b-cdb0-40dd-9f1c-b3f580633a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788427053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1788427053
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2094626030
Short name T200
Test name
Test status
Simulation time 6941769221 ps
CPU time 6.8 seconds
Started Jun 23 06:00:23 PM PDT 24
Finished Jun 23 06:00:30 PM PDT 24
Peak memory 213328 kb
Host smart-e1bb43b3-adbd-4bb1-adde-181bb45f0e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094626030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2094626030
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2250982568
Short name T10
Test name
Test status
Simulation time 23720976715 ps
CPU time 18.27 seconds
Started Jun 23 06:00:23 PM PDT 24
Finished Jun 23 06:00:41 PM PDT 24
Peak memory 205040 kb
Host smart-9891299a-84e6-4dd0-adaa-eb139617edcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250982568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2250982568
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3234579850
Short name T45
Test name
Test status
Simulation time 1087362572 ps
CPU time 3.75 seconds
Started Jun 23 06:00:23 PM PDT 24
Finished Jun 23 06:00:27 PM PDT 24
Peak memory 204740 kb
Host smart-ab3ca700-bc73-46a0-b0e7-fb0732f61f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234579850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3234579850
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.956190019
Short name T33
Test name
Test status
Simulation time 884101276 ps
CPU time 1.01 seconds
Started Jun 23 06:00:30 PM PDT 24
Finished Jun 23 06:00:31 PM PDT 24
Peak memory 204616 kb
Host smart-4d6679f2-068c-460f-9dec-7f052f2cb247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956190019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.956190019
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3600680269
Short name T26
Test name
Test status
Simulation time 17296982236 ps
CPU time 42.83 seconds
Started Jun 23 06:00:22 PM PDT 24
Finished Jun 23 06:01:05 PM PDT 24
Peak memory 204944 kb
Host smart-0eaeea40-cbde-4d9d-8bcb-2052e163b1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600680269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3600680269
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.451478859
Short name T154
Test name
Test status
Simulation time 114629656 ps
CPU time 0.8 seconds
Started Jun 23 06:00:28 PM PDT 24
Finished Jun 23 06:00:30 PM PDT 24
Peak memory 204744 kb
Host smart-b6653682-4123-4615-88d5-4749739e6bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451478859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.451478859
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3864826971
Short name T236
Test name
Test status
Simulation time 5032116345 ps
CPU time 15.1 seconds
Started Jun 23 06:00:17 PM PDT 24
Finished Jun 23 06:00:32 PM PDT 24
Peak memory 205120 kb
Host smart-b2a6ab22-498c-4f75-b4c9-96f596d08d89
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864826971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3864826971
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1265041031
Short name T46
Test name
Test status
Simulation time 903874835 ps
CPU time 1.4 seconds
Started Jun 23 06:00:28 PM PDT 24
Finished Jun 23 06:00:30 PM PDT 24
Peak memory 204704 kb
Host smart-08c49003-3d13-4094-804e-21bd42c2e0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265041031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1265041031
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1537443509
Short name T186
Test name
Test status
Simulation time 157519044 ps
CPU time 0.88 seconds
Started Jun 23 06:00:29 PM PDT 24
Finished Jun 23 06:00:31 PM PDT 24
Peak memory 204548 kb
Host smart-46073aca-2021-4430-879d-6affff0fc1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537443509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1537443509
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3323998056
Short name T198
Test name
Test status
Simulation time 1194206777 ps
CPU time 3.5 seconds
Started Jun 23 06:00:27 PM PDT 24
Finished Jun 23 06:00:31 PM PDT 24
Peak memory 204612 kb
Host smart-78320335-e6d0-45bc-a1f5-c7988b2a4bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323998056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3323998056
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2735878506
Short name T241
Test name
Test status
Simulation time 1554147129 ps
CPU time 3.7 seconds
Started Jun 23 06:00:29 PM PDT 24
Finished Jun 23 06:00:33 PM PDT 24
Peak memory 204560 kb
Host smart-8fc6b4f2-8929-4f12-8389-5bcde0193396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735878506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2735878506
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.896296200
Short name T204
Test name
Test status
Simulation time 359888840 ps
CPU time 0.73 seconds
Started Jun 23 06:00:28 PM PDT 24
Finished Jun 23 06:00:29 PM PDT 24
Peak memory 204580 kb
Host smart-4c74d295-f0e3-4076-ba22-6903f027181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896296200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.896296200
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1374963003
Short name T8
Test name
Test status
Simulation time 586688486 ps
CPU time 2.05 seconds
Started Jun 23 06:00:31 PM PDT 24
Finished Jun 23 06:00:34 PM PDT 24
Peak memory 204608 kb
Host smart-af1f211a-100c-4b2c-9995-2767cdf1b676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374963003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1374963003
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3928113604
Short name T7
Test name
Test status
Simulation time 354848453 ps
CPU time 0.9 seconds
Started Jun 23 06:00:22 PM PDT 24
Finished Jun 23 06:00:23 PM PDT 24
Peak memory 204708 kb
Host smart-0d3c7b7c-f031-4147-934b-a68cc97016eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928113604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3928113604
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1710567417
Short name T18
Test name
Test status
Simulation time 617521250 ps
CPU time 1.8 seconds
Started Jun 23 06:00:19 PM PDT 24
Finished Jun 23 06:00:22 PM PDT 24
Peak memory 204760 kb
Host smart-7b5e26e7-9929-4614-ac5b-ab40fd75514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710567417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1710567417
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.69580185
Short name T20
Test name
Test status
Simulation time 1625360711 ps
CPU time 2.11 seconds
Started Jun 23 06:00:27 PM PDT 24
Finished Jun 23 06:00:29 PM PDT 24
Peak memory 204916 kb
Host smart-ed8f6d6f-892e-42a0-ac27-f1fcc258ba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69580185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.69580185
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3319292922
Short name T14
Test name
Test status
Simulation time 469417725 ps
CPU time 0.84 seconds
Started Jun 23 06:00:27 PM PDT 24
Finished Jun 23 06:00:28 PM PDT 24
Peak memory 204668 kb
Host smart-2c37f95d-9e6d-477c-99bb-f9d2d4a8f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319292922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3319292922
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3764154829
Short name T47
Test name
Test status
Simulation time 259882085 ps
CPU time 1.43 seconds
Started Jun 23 06:00:34 PM PDT 24
Finished Jun 23 06:00:36 PM PDT 24
Peak memory 204776 kb
Host smart-9a46b9d3-2438-4c9b-a146-353166fe5f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764154829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3764154829
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2302227778
Short name T37
Test name
Test status
Simulation time 61708015 ps
CPU time 0.88 seconds
Started Jun 23 06:00:30 PM PDT 24
Finished Jun 23 06:00:32 PM PDT 24
Peak memory 213028 kb
Host smart-4a2088cb-9b93-40ac-8fab-1a471ea214a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302227778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2302227778
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1561523934
Short name T192
Test name
Test status
Simulation time 3740542918 ps
CPU time 3.66 seconds
Started Jun 23 06:00:18 PM PDT 24
Finished Jun 23 06:00:22 PM PDT 24
Peak memory 205196 kb
Host smart-eed319de-fae1-47bd-9c85-17d1e19cf7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561523934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1561523934
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1021267576
Short name T1
Test name
Test status
Simulation time 1446340500 ps
CPU time 2.05 seconds
Started Jun 23 06:00:36 PM PDT 24
Finished Jun 23 06:00:38 PM PDT 24
Peak memory 229224 kb
Host smart-a9058017-ce04-4274-b05b-3c1eb7aab9cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021267576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1021267576
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1269727388
Short name T29
Test name
Test status
Simulation time 447957859 ps
CPU time 1.92 seconds
Started Jun 23 06:00:16 PM PDT 24
Finished Jun 23 06:00:18 PM PDT 24
Peak memory 204568 kb
Host smart-32c0e7d1-8302-4929-80bf-2f47ba1b2206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269727388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1269727388
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2064336485
Short name T170
Test name
Test status
Simulation time 93703698 ps
CPU time 0.79 seconds
Started Jun 23 06:01:03 PM PDT 24
Finished Jun 23 06:01:04 PM PDT 24
Peak memory 204768 kb
Host smart-411cae61-533a-483f-93ee-fcd42da3cd63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064336485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2064336485
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.64113023
Short name T215
Test name
Test status
Simulation time 36363886089 ps
CPU time 51.72 seconds
Started Jun 23 06:01:04 PM PDT 24
Finished Jun 23 06:01:56 PM PDT 24
Peak memory 218852 kb
Host smart-44f0c6ec-45fa-4a03-bb4c-eba8cbd40e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64113023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.64113023
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.447427376
Short name T225
Test name
Test status
Simulation time 1464655967 ps
CPU time 2.24 seconds
Started Jun 23 06:01:01 PM PDT 24
Finished Jun 23 06:01:04 PM PDT 24
Peak memory 205044 kb
Host smart-32e1173e-49ad-4c80-befd-cd24d671b218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447427376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.447427376
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3164959261
Short name T229
Test name
Test status
Simulation time 16686943279 ps
CPU time 5.86 seconds
Started Jun 23 06:01:03 PM PDT 24
Finished Jun 23 06:01:09 PM PDT 24
Peak memory 213404 kb
Host smart-75c6e0e9-a070-4859-b71f-49ef9d4ada96
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164959261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3164959261
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1416270529
Short name T219
Test name
Test status
Simulation time 5453992855 ps
CPU time 15.05 seconds
Started Jun 23 06:01:06 PM PDT 24
Finished Jun 23 06:01:21 PM PDT 24
Peak memory 205132 kb
Host smart-9808bac4-c271-41d2-9b30-f1cc7aa9292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416270529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1416270529
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.228743789
Short name T132
Test name
Test status
Simulation time 93944640 ps
CPU time 0.99 seconds
Started Jun 23 06:01:05 PM PDT 24
Finished Jun 23 06:01:07 PM PDT 24
Peak memory 204808 kb
Host smart-7ffaffd8-4963-41d4-9a12-a6658bda8820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228743789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.228743789
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3951453959
Short name T194
Test name
Test status
Simulation time 17185663919 ps
CPU time 52.76 seconds
Started Jun 23 06:01:02 PM PDT 24
Finished Jun 23 06:01:55 PM PDT 24
Peak memory 213252 kb
Host smart-3bd38001-a9b4-4e58-8b8b-406703a21e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951453959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3951453959
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.4028342200
Short name T199
Test name
Test status
Simulation time 2171026364 ps
CPU time 3.44 seconds
Started Jun 23 06:01:02 PM PDT 24
Finished Jun 23 06:01:06 PM PDT 24
Peak memory 205132 kb
Host smart-ebc8663b-22c4-4459-9cb5-0714070f31b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028342200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.4028342200
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.962130248
Short name T96
Test name
Test status
Simulation time 4678247068 ps
CPU time 12.87 seconds
Started Jun 23 06:01:05 PM PDT 24
Finished Jun 23 06:01:18 PM PDT 24
Peak memory 205196 kb
Host smart-fe1a2b78-1f5c-4f87-9dc4-5273c6128b21
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=962130248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.962130248
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1626099173
Short name T185
Test name
Test status
Simulation time 1632468028 ps
CPU time 5.11 seconds
Started Jun 23 06:01:02 PM PDT 24
Finished Jun 23 06:01:08 PM PDT 24
Peak memory 205052 kb
Host smart-0429a9e2-fe01-4573-b25a-3ae8101fb2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626099173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1626099173
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2619550299
Short name T169
Test name
Test status
Simulation time 54944888 ps
CPU time 0.73 seconds
Started Jun 23 06:01:07 PM PDT 24
Finished Jun 23 06:01:08 PM PDT 24
Peak memory 204776 kb
Host smart-58008957-c67c-49b7-9298-fe84e9b1c61e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619550299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2619550299
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.4189412186
Short name T232
Test name
Test status
Simulation time 5101371936 ps
CPU time 9.61 seconds
Started Jun 23 06:01:15 PM PDT 24
Finished Jun 23 06:01:25 PM PDT 24
Peak memory 213344 kb
Host smart-2ccac02a-2c0d-4601-9d62-f851cb31fb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189412186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4189412186
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.482334925
Short name T207
Test name
Test status
Simulation time 8324697384 ps
CPU time 12.18 seconds
Started Jun 23 06:01:07 PM PDT 24
Finished Jun 23 06:01:20 PM PDT 24
Peak memory 205284 kb
Host smart-284bd456-fc8d-4483-ad76-5b9c3af4c4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482334925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.482334925
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1087541516
Short name T79
Test name
Test status
Simulation time 9104826039 ps
CPU time 12.73 seconds
Started Jun 23 06:01:08 PM PDT 24
Finished Jun 23 06:01:21 PM PDT 24
Peak memory 205132 kb
Host smart-48b920e5-19c7-47f2-b2ab-2ca798a69d78
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087541516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1087541516
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.4138856831
Short name T246
Test name
Test status
Simulation time 8300787238 ps
CPU time 6.23 seconds
Started Jun 23 06:01:05 PM PDT 24
Finished Jun 23 06:01:12 PM PDT 24
Peak memory 205156 kb
Host smart-7bd35c94-fa31-4a5b-bcd8-b448302c83b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138856831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.4138856831
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.259442823
Short name T159
Test name
Test status
Simulation time 70014712 ps
CPU time 0.69 seconds
Started Jun 23 06:01:08 PM PDT 24
Finished Jun 23 06:01:09 PM PDT 24
Peak memory 204804 kb
Host smart-54d1493e-73d0-43a9-bb90-2650602d9265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259442823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.259442823
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.655989287
Short name T94
Test name
Test status
Simulation time 31050788956 ps
CPU time 81.48 seconds
Started Jun 23 06:01:06 PM PDT 24
Finished Jun 23 06:02:28 PM PDT 24
Peak memory 213400 kb
Host smart-04fbfe24-23b6-46bf-b312-9e81ef43d68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655989287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.655989287
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3215125261
Short name T212
Test name
Test status
Simulation time 19479345474 ps
CPU time 12.26 seconds
Started Jun 23 06:01:04 PM PDT 24
Finished Jun 23 06:01:16 PM PDT 24
Peak memory 205204 kb
Host smart-ca83c41f-3338-42f5-84a8-00f2820f3b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215125261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3215125261
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2222170183
Short name T196
Test name
Test status
Simulation time 2797519620 ps
CPU time 6.8 seconds
Started Jun 23 06:01:09 PM PDT 24
Finished Jun 23 06:01:16 PM PDT 24
Peak memory 205136 kb
Host smart-ddb0745d-fb61-4046-8fa3-63a7e67d138e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2222170183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2222170183
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.4011548642
Short name T248
Test name
Test status
Simulation time 13674334153 ps
CPU time 32.67 seconds
Started Jun 23 06:01:05 PM PDT 24
Finished Jun 23 06:01:38 PM PDT 24
Peak memory 205152 kb
Host smart-7f621827-a24b-49c8-8ebe-02ad4dd6f5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011548642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.4011548642
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1901020020
Short name T187
Test name
Test status
Simulation time 63914111 ps
CPU time 0.79 seconds
Started Jun 23 06:01:11 PM PDT 24
Finished Jun 23 06:01:12 PM PDT 24
Peak memory 204804 kb
Host smart-d0736d14-80db-4aec-b6aa-5a0f88ca33ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901020020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1901020020
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.193621284
Short name T25
Test name
Test status
Simulation time 21637438615 ps
CPU time 48.46 seconds
Started Jun 23 06:01:10 PM PDT 24
Finished Jun 23 06:01:59 PM PDT 24
Peak memory 213352 kb
Host smart-a3d97b18-e26e-40b7-b1ac-f66007708c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193621284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.193621284
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4168794419
Short name T15
Test name
Test status
Simulation time 3117164129 ps
CPU time 6.3 seconds
Started Jun 23 06:01:15 PM PDT 24
Finished Jun 23 06:01:21 PM PDT 24
Peak memory 205152 kb
Host smart-f56bfa17-c4fb-44bf-805e-37853ef041d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168794419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4168794419
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2893162200
Short name T208
Test name
Test status
Simulation time 3483830807 ps
CPU time 10.1 seconds
Started Jun 23 06:01:14 PM PDT 24
Finished Jun 23 06:01:25 PM PDT 24
Peak memory 205152 kb
Host smart-18bc6c97-9cfc-4a19-947d-80b0ec1d4a27
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893162200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2893162200
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1082307469
Short name T247
Test name
Test status
Simulation time 4107493624 ps
CPU time 2.87 seconds
Started Jun 23 06:01:08 PM PDT 24
Finished Jun 23 06:01:11 PM PDT 24
Peak memory 205204 kb
Host smart-4a72bcce-1eda-49b1-86f6-6e13e47f991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082307469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1082307469
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.167514458
Short name T64
Test name
Test status
Simulation time 51829630 ps
CPU time 0.79 seconds
Started Jun 23 06:01:11 PM PDT 24
Finished Jun 23 06:01:12 PM PDT 24
Peak memory 204804 kb
Host smart-f86c290a-f7fe-44b5-b148-5981ea99e78e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167514458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.167514458
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1178026781
Short name T233
Test name
Test status
Simulation time 23255716953 ps
CPU time 9.72 seconds
Started Jun 23 06:01:09 PM PDT 24
Finished Jun 23 06:01:19 PM PDT 24
Peak memory 213300 kb
Host smart-44b1e0c1-1eb0-402c-9fe6-f4f3091053fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178026781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1178026781
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1086187182
Short name T201
Test name
Test status
Simulation time 6228119573 ps
CPU time 4.72 seconds
Started Jun 23 06:01:13 PM PDT 24
Finished Jun 23 06:01:18 PM PDT 24
Peak memory 205184 kb
Host smart-44ea00e3-4094-4470-9763-266ca5525156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086187182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1086187182
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.92506651
Short name T239
Test name
Test status
Simulation time 3064236056 ps
CPU time 5.28 seconds
Started Jun 23 06:01:13 PM PDT 24
Finished Jun 23 06:01:19 PM PDT 24
Peak memory 205176 kb
Host smart-6272ebea-ea14-48a3-9560-a84548087a76
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92506651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl
_access.92506651
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1178755474
Short name T263
Test name
Test status
Simulation time 19247414013 ps
CPU time 50.17 seconds
Started Jun 23 06:01:12 PM PDT 24
Finished Jun 23 06:02:02 PM PDT 24
Peak memory 205168 kb
Host smart-e0749da2-64ec-4f39-8faa-0c36a529dcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178755474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1178755474
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2276906772
Short name T161
Test name
Test status
Simulation time 137852756 ps
CPU time 0.8 seconds
Started Jun 23 06:01:17 PM PDT 24
Finished Jun 23 06:01:18 PM PDT 24
Peak memory 204772 kb
Host smart-d7b011bc-532d-4358-929d-3734efe06a7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276906772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2276906772
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.500528523
Short name T268
Test name
Test status
Simulation time 5641790323 ps
CPU time 2.06 seconds
Started Jun 23 06:01:16 PM PDT 24
Finished Jun 23 06:01:18 PM PDT 24
Peak memory 205148 kb
Host smart-836468d5-460e-451a-83e9-58ec254cedc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500528523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.500528523
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.424515117
Short name T226
Test name
Test status
Simulation time 2233780399 ps
CPU time 4.4 seconds
Started Jun 23 06:01:10 PM PDT 24
Finished Jun 23 06:01:14 PM PDT 24
Peak memory 205132 kb
Host smart-b7385d9a-38e9-4394-8553-207849d7fa2d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424515117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.424515117
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2890061012
Short name T238
Test name
Test status
Simulation time 2791791754 ps
CPU time 6.03 seconds
Started Jun 23 06:01:10 PM PDT 24
Finished Jun 23 06:01:17 PM PDT 24
Peak memory 205164 kb
Host smart-06ca89c0-0f0d-46f2-a689-9348e4c0db86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890061012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2890061012
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2095714441
Short name T39
Test name
Test status
Simulation time 11822902248 ps
CPU time 9.48 seconds
Started Jun 23 06:01:17 PM PDT 24
Finished Jun 23 06:01:27 PM PDT 24
Peak memory 213192 kb
Host smart-4d16844f-0f34-42bf-b508-f91a0b8cebe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095714441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2095714441
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.71181124
Short name T168
Test name
Test status
Simulation time 48798125 ps
CPU time 0.75 seconds
Started Jun 23 06:01:14 PM PDT 24
Finished Jun 23 06:01:15 PM PDT 24
Peak memory 204852 kb
Host smart-2739a6e0-f193-4ed4-a243-04001a0d0888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71181124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.71181124
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3962557590
Short name T264
Test name
Test status
Simulation time 26549589302 ps
CPU time 16.78 seconds
Started Jun 23 06:01:16 PM PDT 24
Finished Jun 23 06:01:33 PM PDT 24
Peak memory 213312 kb
Host smart-f39f8c91-7b64-40fe-b795-9bb956336c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962557590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3962557590
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3594944088
Short name T254
Test name
Test status
Simulation time 1974855233 ps
CPU time 6.23 seconds
Started Jun 23 06:01:18 PM PDT 24
Finished Jun 23 06:01:24 PM PDT 24
Peak memory 205124 kb
Host smart-e63550c2-227d-4a4d-b1b6-4f7fc5be7b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594944088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3594944088
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2484595218
Short name T259
Test name
Test status
Simulation time 1708126013 ps
CPU time 5.69 seconds
Started Jun 23 06:01:17 PM PDT 24
Finished Jun 23 06:01:23 PM PDT 24
Peak memory 204992 kb
Host smart-8cc4d1f7-9e6a-465a-9e96-a4849fc0611f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484595218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2484595218
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.45629732
Short name T267
Test name
Test status
Simulation time 1824868852 ps
CPU time 3.99 seconds
Started Jun 23 06:01:14 PM PDT 24
Finished Jun 23 06:01:19 PM PDT 24
Peak memory 205080 kb
Host smart-badae0b8-955c-4166-9b6c-8c4b7b9e65b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45629732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.45629732
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1533243345
Short name T182
Test name
Test status
Simulation time 99929168 ps
CPU time 0.8 seconds
Started Jun 23 06:01:22 PM PDT 24
Finished Jun 23 06:01:23 PM PDT 24
Peak memory 204760 kb
Host smart-2e809945-3e88-42ba-8f31-ee5cfe9e4f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533243345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1533243345
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.4181533518
Short name T205
Test name
Test status
Simulation time 61875832856 ps
CPU time 99.7 seconds
Started Jun 23 06:01:22 PM PDT 24
Finished Jun 23 06:03:02 PM PDT 24
Peak memory 213424 kb
Host smart-2d4b0773-8731-474e-a54f-7aeeb4760750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181533518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.4181533518
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2962573255
Short name T231
Test name
Test status
Simulation time 11078045437 ps
CPU time 10.06 seconds
Started Jun 23 06:01:20 PM PDT 24
Finished Jun 23 06:01:30 PM PDT 24
Peak memory 214924 kb
Host smart-d5d652ec-a290-4d9f-b432-9231ecb5ff0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962573255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2962573255
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2027010546
Short name T234
Test name
Test status
Simulation time 7433396890 ps
CPU time 5.9 seconds
Started Jun 23 06:01:17 PM PDT 24
Finished Jun 23 06:01:23 PM PDT 24
Peak memory 205100 kb
Host smart-48b90aaa-7975-49cc-b6d1-311236a4971e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2027010546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2027010546
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1251384518
Short name T242
Test name
Test status
Simulation time 1528858100 ps
CPU time 1.94 seconds
Started Jun 23 06:01:16 PM PDT 24
Finished Jun 23 06:01:18 PM PDT 24
Peak memory 205084 kb
Host smart-aaf7d1d9-1829-4298-b514-d5cda69885d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251384518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1251384518
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3047396789
Short name T163
Test name
Test status
Simulation time 31804593 ps
CPU time 0.75 seconds
Started Jun 23 06:01:20 PM PDT 24
Finished Jun 23 06:01:21 PM PDT 24
Peak memory 204760 kb
Host smart-4eecee91-c6db-4dd3-99a8-0956b5b15135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047396789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3047396789
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2080853111
Short name T227
Test name
Test status
Simulation time 1494147255 ps
CPU time 2.96 seconds
Started Jun 23 06:01:19 PM PDT 24
Finished Jun 23 06:01:22 PM PDT 24
Peak memory 205092 kb
Host smart-de1900f1-040e-47d2-90e3-ac7e067381ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080853111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2080853111
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.934256988
Short name T244
Test name
Test status
Simulation time 4336434078 ps
CPU time 6.56 seconds
Started Jun 23 06:01:21 PM PDT 24
Finished Jun 23 06:01:27 PM PDT 24
Peak memory 205152 kb
Host smart-e1ef9b0c-1976-4f48-bfdc-6a1814b08ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934256988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.934256988
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3190469117
Short name T30
Test name
Test status
Simulation time 3827915563 ps
CPU time 3.81 seconds
Started Jun 23 06:01:22 PM PDT 24
Finished Jun 23 06:01:26 PM PDT 24
Peak memory 205188 kb
Host smart-e1fcc6d7-53e3-4a46-8f31-69820d286978
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190469117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3190469117
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2506753507
Short name T206
Test name
Test status
Simulation time 2527093317 ps
CPU time 2.89 seconds
Started Jun 23 06:01:20 PM PDT 24
Finished Jun 23 06:01:24 PM PDT 24
Peak memory 205184 kb
Host smart-50561d50-9849-4f0e-be88-883e4ac8cbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506753507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2506753507
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.1789094292
Short name T5
Test name
Test status
Simulation time 6159545813 ps
CPU time 4.74 seconds
Started Jun 23 06:01:21 PM PDT 24
Finished Jun 23 06:01:26 PM PDT 24
Peak memory 204996 kb
Host smart-16a9ba41-de02-4780-ad40-6dc5d1f7dc9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789094292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1789094292
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.439307228
Short name T77
Test name
Test status
Simulation time 219860955 ps
CPU time 0.72 seconds
Started Jun 23 06:00:37 PM PDT 24
Finished Jun 23 06:00:38 PM PDT 24
Peak memory 204772 kb
Host smart-48b80aa8-a4ae-41a5-b57b-ebe72efe3118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439307228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.439307228
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1352880263
Short name T217
Test name
Test status
Simulation time 5968630477 ps
CPU time 11.6 seconds
Started Jun 23 06:00:36 PM PDT 24
Finished Jun 23 06:00:48 PM PDT 24
Peak memory 213372 kb
Host smart-265de3b5-7d70-44c0-a8f3-7e6b16ea9072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352880263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1352880263
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1822421010
Short name T3
Test name
Test status
Simulation time 5372180337 ps
CPU time 14.29 seconds
Started Jun 23 06:00:37 PM PDT 24
Finished Jun 23 06:00:51 PM PDT 24
Peak memory 205136 kb
Host smart-0ef136fa-e504-45e1-9516-43628619754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822421010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1822421010
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3013777594
Short name T230
Test name
Test status
Simulation time 3403854769 ps
CPU time 3.23 seconds
Started Jun 23 06:00:38 PM PDT 24
Finished Jun 23 06:00:41 PM PDT 24
Peak memory 205132 kb
Host smart-f51f1cb0-04a7-48b4-a6bb-925882ee6910
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3013777594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3013777594
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2602962887
Short name T59
Test name
Test status
Simulation time 127746883 ps
CPU time 0.79 seconds
Started Jun 23 06:00:39 PM PDT 24
Finished Jun 23 06:00:40 PM PDT 24
Peak memory 204620 kb
Host smart-42a5fd45-c0eb-4392-ae2c-4da7943aa9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602962887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2602962887
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.466483495
Short name T9
Test name
Test status
Simulation time 11829975457 ps
CPU time 33.26 seconds
Started Jun 23 06:00:36 PM PDT 24
Finished Jun 23 06:01:10 PM PDT 24
Peak memory 205060 kb
Host smart-e18cdf7e-0c03-43f7-b684-694471e0d949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466483495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.466483495
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1980486519
Short name T67
Test name
Test status
Simulation time 1476394717 ps
CPU time 1.63 seconds
Started Jun 23 06:00:38 PM PDT 24
Finished Jun 23 06:00:40 PM PDT 24
Peak memory 229628 kb
Host smart-a3fe4b80-b2bd-420c-9bba-1646c2b26236
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980486519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1980486519
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.4215433899
Short name T256
Test name
Test status
Simulation time 5922513876 ps
CPU time 15.4 seconds
Started Jun 23 06:00:39 PM PDT 24
Finished Jun 23 06:00:55 PM PDT 24
Peak memory 204944 kb
Host smart-5a068e09-e942-4fcd-9a3f-d0661c8327af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215433899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.4215433899
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.978113109
Short name T174
Test name
Test status
Simulation time 128004048 ps
CPU time 1.04 seconds
Started Jun 23 06:01:27 PM PDT 24
Finished Jun 23 06:01:28 PM PDT 24
Peak memory 204804 kb
Host smart-4215b997-38e0-4194-8e38-0c80bdd26d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978113109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.978113109
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.68210358
Short name T27
Test name
Test status
Simulation time 16895821115 ps
CPU time 45.72 seconds
Started Jun 23 06:01:25 PM PDT 24
Finished Jun 23 06:02:11 PM PDT 24
Peak memory 204976 kb
Host smart-2f57e146-1df2-43de-b412-6f8b08b1f0ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68210358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.68210358
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3928772164
Short name T252
Test name
Test status
Simulation time 210275777 ps
CPU time 0.76 seconds
Started Jun 23 06:01:24 PM PDT 24
Finished Jun 23 06:01:25 PM PDT 24
Peak memory 204812 kb
Host smart-ba413fcf-d8e8-4180-9252-096eedb6470f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928772164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3928772164
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3521739985
Short name T152
Test name
Test status
Simulation time 3267033094 ps
CPU time 10.13 seconds
Started Jun 23 06:01:23 PM PDT 24
Finished Jun 23 06:01:34 PM PDT 24
Peak memory 205136 kb
Host smart-fb341181-d5a7-4aa2-91b2-4bbf2c5645c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521739985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3521739985
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.213339867
Short name T172
Test name
Test status
Simulation time 164470512 ps
CPU time 0.77 seconds
Started Jun 23 06:01:26 PM PDT 24
Finished Jun 23 06:01:27 PM PDT 24
Peak memory 204800 kb
Host smart-4158bee5-e9e5-4d0c-80c9-4cb3753aa70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213339867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.213339867
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3425720043
Short name T95
Test name
Test status
Simulation time 93422389 ps
CPU time 0.79 seconds
Started Jun 23 06:01:27 PM PDT 24
Finished Jun 23 06:01:28 PM PDT 24
Peak memory 204796 kb
Host smart-e928bf7d-1c0f-4d64-b7b7-33200c5568f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425720043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3425720043
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.2374271058
Short name T43
Test name
Test status
Simulation time 22358443566 ps
CPU time 47.98 seconds
Started Jun 23 06:01:28 PM PDT 24
Finished Jun 23 06:02:16 PM PDT 24
Peak memory 204928 kb
Host smart-091b29e0-d9ac-4894-816d-84ec6c3049cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374271058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2374271058
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1265427668
Short name T162
Test name
Test status
Simulation time 45589827 ps
CPU time 0.74 seconds
Started Jun 23 06:01:26 PM PDT 24
Finished Jun 23 06:01:27 PM PDT 24
Peak memory 204852 kb
Host smart-9ddd94eb-7261-43ed-b2df-0a1cc3d19fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265427668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1265427668
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.3505628080
Short name T150
Test name
Test status
Simulation time 23195222247 ps
CPU time 12.34 seconds
Started Jun 23 06:01:28 PM PDT 24
Finished Jun 23 06:01:40 PM PDT 24
Peak memory 204980 kb
Host smart-5e504951-7b9f-47fe-8d7f-dc4515dc3ccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505628080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.3505628080
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1722814980
Short name T166
Test name
Test status
Simulation time 67712659 ps
CPU time 0.84 seconds
Started Jun 23 06:01:27 PM PDT 24
Finished Jun 23 06:01:28 PM PDT 24
Peak memory 204796 kb
Host smart-9266c949-6ff4-4d9b-b37c-776a1968a8d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722814980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1722814980
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2228032256
Short name T63
Test name
Test status
Simulation time 163592436 ps
CPU time 1.08 seconds
Started Jun 23 06:01:26 PM PDT 24
Finished Jun 23 06:01:27 PM PDT 24
Peak memory 204812 kb
Host smart-722fb6f9-07b7-4c61-ba94-6c7e1eaea7c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228032256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2228032256
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2809261626
Short name T164
Test name
Test status
Simulation time 138126555 ps
CPU time 0.84 seconds
Started Jun 23 06:01:32 PM PDT 24
Finished Jun 23 06:01:34 PM PDT 24
Peak memory 204824 kb
Host smart-c12fd8cd-2db7-40aa-a268-03472fb6147e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809261626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2809261626
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1029769905
Short name T257
Test name
Test status
Simulation time 346390659 ps
CPU time 0.71 seconds
Started Jun 23 06:01:32 PM PDT 24
Finished Jun 23 06:01:33 PM PDT 24
Peak memory 204812 kb
Host smart-7ebabc3d-6f6e-418e-b2f1-088c2c8c922a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029769905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1029769905
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2414040881
Short name T65
Test name
Test status
Simulation time 152216047 ps
CPU time 1.03 seconds
Started Jun 23 06:01:34 PM PDT 24
Finished Jun 23 06:01:35 PM PDT 24
Peak memory 204796 kb
Host smart-43a5641a-4dd9-401a-b762-088d2ec5f899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414040881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2414040881
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1721199002
Short name T178
Test name
Test status
Simulation time 45035413 ps
CPU time 0.8 seconds
Started Jun 23 06:00:43 PM PDT 24
Finished Jun 23 06:00:44 PM PDT 24
Peak memory 204804 kb
Host smart-46a04f9b-3fdf-4a46-aefe-7744db6e5bdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721199002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1721199002
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2659043882
Short name T197
Test name
Test status
Simulation time 19766066901 ps
CPU time 40.27 seconds
Started Jun 23 06:00:39 PM PDT 24
Finished Jun 23 06:01:20 PM PDT 24
Peak memory 213348 kb
Host smart-b3a8249b-a56a-437c-b65f-7df0891ab57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659043882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2659043882
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3911095329
Short name T191
Test name
Test status
Simulation time 8680710504 ps
CPU time 6.61 seconds
Started Jun 23 06:00:39 PM PDT 24
Finished Jun 23 06:00:46 PM PDT 24
Peak memory 205188 kb
Host smart-a91396bb-89d3-4fb4-840b-4919a58770aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911095329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3911095329
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3593245324
Short name T266
Test name
Test status
Simulation time 3696181289 ps
CPU time 10.12 seconds
Started Jun 23 06:00:39 PM PDT 24
Finished Jun 23 06:00:49 PM PDT 24
Peak memory 205228 kb
Host smart-8b9f72cb-4ff8-4737-90bc-235fe716db84
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593245324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3593245324
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3793519491
Short name T66
Test name
Test status
Simulation time 683985537 ps
CPU time 2.27 seconds
Started Jun 23 06:00:37 PM PDT 24
Finished Jun 23 06:00:39 PM PDT 24
Peak memory 204552 kb
Host smart-6058df26-4f7a-43fb-90a8-8a260cca293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793519491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3793519491
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1943926552
Short name T218
Test name
Test status
Simulation time 1393549767 ps
CPU time 2.21 seconds
Started Jun 23 06:00:40 PM PDT 24
Finished Jun 23 06:00:42 PM PDT 24
Peak memory 205068 kb
Host smart-a916df94-07e8-43b5-8d22-6074e35ff139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943926552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1943926552
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.2778895851
Short name T146
Test name
Test status
Simulation time 22707909721 ps
CPU time 35.5 seconds
Started Jun 23 06:00:41 PM PDT 24
Finished Jun 23 06:01:17 PM PDT 24
Peak memory 205024 kb
Host smart-292f069e-7bdf-470a-922a-f2eb6f734a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778895851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2778895851
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.173901857
Short name T223
Test name
Test status
Simulation time 99706062 ps
CPU time 0.82 seconds
Started Jun 23 06:01:33 PM PDT 24
Finished Jun 23 06:01:34 PM PDT 24
Peak memory 204768 kb
Host smart-23264d9a-70c8-44ee-acda-8cdf6c5a08c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173901857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.173901857
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3890372011
Short name T243
Test name
Test status
Simulation time 18305851676 ps
CPU time 20.54 seconds
Started Jun 23 06:01:31 PM PDT 24
Finished Jun 23 06:01:52 PM PDT 24
Peak memory 204996 kb
Host smart-001f37c5-2c3d-40f5-bc93-4c5778fa4430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890372011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3890372011
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1605044477
Short name T171
Test name
Test status
Simulation time 79846529 ps
CPU time 0.75 seconds
Started Jun 23 06:01:32 PM PDT 24
Finished Jun 23 06:01:33 PM PDT 24
Peak memory 204812 kb
Host smart-3912b2e9-2a61-42e5-907b-8d956d465dee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605044477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1605044477
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.412402808
Short name T183
Test name
Test status
Simulation time 43368260 ps
CPU time 0.73 seconds
Started Jun 23 06:01:32 PM PDT 24
Finished Jun 23 06:01:33 PM PDT 24
Peak memory 204808 kb
Host smart-5f13a030-c1c4-476a-92ed-4ef6ad02d3ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412402808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.412402808
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3298219473
Short name T97
Test name
Test status
Simulation time 51153017 ps
CPU time 0.85 seconds
Started Jun 23 06:01:34 PM PDT 24
Finished Jun 23 06:01:35 PM PDT 24
Peak memory 204772 kb
Host smart-cbb89227-7c7d-417d-a367-1fb68cabce21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298219473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3298219473
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3208654467
Short name T160
Test name
Test status
Simulation time 86220314 ps
CPU time 0.71 seconds
Started Jun 23 06:01:28 PM PDT 24
Finished Jun 23 06:01:29 PM PDT 24
Peak memory 204772 kb
Host smart-f7f1d1ad-463b-4190-b6cb-da55a6c36e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208654467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3208654467
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2448308980
Short name T151
Test name
Test status
Simulation time 29484250509 ps
CPU time 18.57 seconds
Started Jun 23 06:01:34 PM PDT 24
Finished Jun 23 06:01:53 PM PDT 24
Peak memory 213168 kb
Host smart-fdf0faa6-82e5-4487-96d4-f6ec218ccddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448308980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2448308980
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3448678943
Short name T76
Test name
Test status
Simulation time 71766785 ps
CPU time 0.75 seconds
Started Jun 23 06:01:31 PM PDT 24
Finished Jun 23 06:01:32 PM PDT 24
Peak memory 204812 kb
Host smart-8018f0bd-26bb-4703-902b-cffd71343552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448678943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3448678943
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.1053073115
Short name T84
Test name
Test status
Simulation time 11576293916 ps
CPU time 10.97 seconds
Started Jun 23 06:01:33 PM PDT 24
Finished Jun 23 06:01:45 PM PDT 24
Peak memory 204984 kb
Host smart-2f396b44-4585-4d3e-adbe-75b571d53383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053073115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1053073115
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1517801289
Short name T179
Test name
Test status
Simulation time 117499715 ps
CPU time 0.92 seconds
Started Jun 23 06:01:31 PM PDT 24
Finished Jun 23 06:01:32 PM PDT 24
Peak memory 204768 kb
Host smart-57764f80-16f5-40d3-80ad-0cf4de881dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517801289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1517801289
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.660112811
Short name T176
Test name
Test status
Simulation time 191494253 ps
CPU time 0.8 seconds
Started Jun 23 06:01:31 PM PDT 24
Finished Jun 23 06:01:32 PM PDT 24
Peak memory 204780 kb
Host smart-afecd13e-32b8-4e0e-8a50-bab21824c134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660112811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.660112811
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1214771790
Short name T58
Test name
Test status
Simulation time 43157830 ps
CPU time 0.75 seconds
Started Jun 23 06:01:40 PM PDT 24
Finished Jun 23 06:01:41 PM PDT 24
Peak memory 204800 kb
Host smart-f011fea6-1071-49bf-a175-b035775cc569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214771790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1214771790
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3416487124
Short name T261
Test name
Test status
Simulation time 66893767 ps
CPU time 0.78 seconds
Started Jun 23 06:01:38 PM PDT 24
Finished Jun 23 06:01:39 PM PDT 24
Peak memory 204808 kb
Host smart-83f3c569-db43-49ed-8d45-b6c4bc9ca8f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416487124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3416487124
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3477534625
Short name T175
Test name
Test status
Simulation time 111691415 ps
CPU time 0.75 seconds
Started Jun 23 06:00:43 PM PDT 24
Finished Jun 23 06:00:44 PM PDT 24
Peak memory 204752 kb
Host smart-740d1793-ec3f-4c08-817f-9068e77875fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477534625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3477534625
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.4121142822
Short name T260
Test name
Test status
Simulation time 56792685353 ps
CPU time 153.54 seconds
Started Jun 23 06:00:44 PM PDT 24
Finished Jun 23 06:03:18 PM PDT 24
Peak memory 213336 kb
Host smart-8885c257-06d6-404f-b073-74391b12b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121142822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.4121142822
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.299906056
Short name T262
Test name
Test status
Simulation time 2288721063 ps
CPU time 7.67 seconds
Started Jun 23 06:00:43 PM PDT 24
Finished Jun 23 06:00:51 PM PDT 24
Peak memory 205192 kb
Host smart-6715ea55-59dc-450b-9090-56f28dcca932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299906056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.299906056
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3725936389
Short name T251
Test name
Test status
Simulation time 2403822975 ps
CPU time 6.97 seconds
Started Jun 23 06:00:43 PM PDT 24
Finished Jun 23 06:00:50 PM PDT 24
Peak memory 205136 kb
Host smart-0ab9a1f2-4f71-48a9-8950-996ca302632e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725936389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3725936389
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.929217402
Short name T22
Test name
Test status
Simulation time 161475566 ps
CPU time 0.85 seconds
Started Jun 23 06:00:41 PM PDT 24
Finished Jun 23 06:00:42 PM PDT 24
Peak memory 204520 kb
Host smart-4e146170-fdac-4a48-b1e8-8ee541ebe52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929217402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.929217402
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2895667728
Short name T265
Test name
Test status
Simulation time 2540890086 ps
CPU time 4.18 seconds
Started Jun 23 06:00:42 PM PDT 24
Finished Jun 23 06:00:46 PM PDT 24
Peak memory 205104 kb
Host smart-a54a4df2-53c4-45e0-b112-35ee1f2c1cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895667728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2895667728
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1629468345
Short name T68
Test name
Test status
Simulation time 2832308962 ps
CPU time 4.74 seconds
Started Jun 23 06:00:40 PM PDT 24
Finished Jun 23 06:00:45 PM PDT 24
Peak memory 228972 kb
Host smart-e3dbdc16-e00c-48e6-bd32-bcc34bf1a683
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629468345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1629468345
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.579687483
Short name T249
Test name
Test status
Simulation time 102746256 ps
CPU time 0.72 seconds
Started Jun 23 06:01:38 PM PDT 24
Finished Jun 23 06:01:39 PM PDT 24
Peak memory 204808 kb
Host smart-9c526f18-6425-4071-905a-8433412f2fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579687483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.579687483
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.19591652
Short name T156
Test name
Test status
Simulation time 42694321 ps
CPU time 0.75 seconds
Started Jun 23 06:01:39 PM PDT 24
Finished Jun 23 06:01:40 PM PDT 24
Peak memory 204828 kb
Host smart-d40672e8-88d9-40b2-a36c-65a3602faba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19591652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.19591652
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.2923543644
Short name T147
Test name
Test status
Simulation time 18874183261 ps
CPU time 27.19 seconds
Started Jun 23 06:01:38 PM PDT 24
Finished Jun 23 06:02:05 PM PDT 24
Peak memory 205032 kb
Host smart-73287dd9-dabb-451e-8bac-714ed9f838a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923543644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.2923543644
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.663955505
Short name T158
Test name
Test status
Simulation time 106797057 ps
CPU time 0.78 seconds
Started Jun 23 06:01:38 PM PDT 24
Finished Jun 23 06:01:39 PM PDT 24
Peak memory 204808 kb
Host smart-e99a901e-5aab-4962-b8b0-d9db8c8f1f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663955505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.663955505
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3368221650
Short name T35
Test name
Test status
Simulation time 7329354777 ps
CPU time 2.81 seconds
Started Jun 23 06:01:39 PM PDT 24
Finished Jun 23 06:01:43 PM PDT 24
Peak memory 204968 kb
Host smart-79ae5c45-cb0e-4f39-9732-92450474881f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368221650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3368221650
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3100480015
Short name T167
Test name
Test status
Simulation time 32391873 ps
CPU time 0.73 seconds
Started Jun 23 06:01:37 PM PDT 24
Finished Jun 23 06:01:38 PM PDT 24
Peak memory 204816 kb
Host smart-6cf9e615-e929-44f8-bca5-b6964a429712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100480015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3100480015
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.886477978
Short name T44
Test name
Test status
Simulation time 31245523249 ps
CPU time 42.59 seconds
Started Jun 23 06:01:37 PM PDT 24
Finished Jun 23 06:02:20 PM PDT 24
Peak memory 205004 kb
Host smart-bdc88a9c-a0a1-434d-9399-06e0e63e69aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886477978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.886477978
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1603677420
Short name T177
Test name
Test status
Simulation time 88690688 ps
CPU time 0.79 seconds
Started Jun 23 06:01:36 PM PDT 24
Finished Jun 23 06:01:37 PM PDT 24
Peak memory 204736 kb
Host smart-149f7d95-80c8-4e48-88b0-128bf92f7a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603677420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1603677420
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.854688381
Short name T155
Test name
Test status
Simulation time 15956023386 ps
CPU time 40.99 seconds
Started Jun 23 06:01:36 PM PDT 24
Finished Jun 23 06:02:18 PM PDT 24
Peak memory 204980 kb
Host smart-096427a4-c570-4cb2-9b4d-a118a4cfd5d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854688381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.854688381
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.843989535
Short name T181
Test name
Test status
Simulation time 140921269 ps
CPU time 0.76 seconds
Started Jun 23 06:01:39 PM PDT 24
Finished Jun 23 06:01:40 PM PDT 24
Peak memory 204780 kb
Host smart-4307b41b-3448-42ea-ae0d-763cb245f882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843989535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.843989535
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1648209692
Short name T51
Test name
Test status
Simulation time 43421427 ps
CPU time 0.76 seconds
Started Jun 23 06:01:45 PM PDT 24
Finished Jun 23 06:01:46 PM PDT 24
Peak memory 204828 kb
Host smart-76658bff-c9fe-44db-841b-117b805163cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648209692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1648209692
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.3930158113
Short name T149
Test name
Test status
Simulation time 20756370276 ps
CPU time 14.87 seconds
Started Jun 23 06:01:40 PM PDT 24
Finished Jun 23 06:01:55 PM PDT 24
Peak memory 213180 kb
Host smart-4f173525-6eb2-494d-99d4-b8dc97d7a34d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930158113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3930158113
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3816917781
Short name T157
Test name
Test status
Simulation time 53082234 ps
CPU time 0.79 seconds
Started Jun 23 06:01:44 PM PDT 24
Finished Jun 23 06:01:45 PM PDT 24
Peak memory 204812 kb
Host smart-185d6881-090c-4746-b422-034163ce70d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816917781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3816917781
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1744217296
Short name T255
Test name
Test status
Simulation time 42596321 ps
CPU time 0.72 seconds
Started Jun 23 06:01:43 PM PDT 24
Finished Jun 23 06:01:44 PM PDT 24
Peak memory 204744 kb
Host smart-e78b9ed1-2a93-4aff-9ef1-9e9c5a91b09c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744217296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1744217296
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3223352555
Short name T173
Test name
Test status
Simulation time 105830385 ps
CPU time 0.92 seconds
Started Jun 23 06:01:43 PM PDT 24
Finished Jun 23 06:01:44 PM PDT 24
Peak memory 204780 kb
Host smart-c7b95591-5cdc-4c82-ae59-997edf0c4205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223352555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3223352555
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3159462351
Short name T78
Test name
Test status
Simulation time 33999450 ps
CPU time 0.73 seconds
Started Jun 23 06:00:46 PM PDT 24
Finished Jun 23 06:00:47 PM PDT 24
Peak memory 204808 kb
Host smart-67a68622-3b20-40cd-8c9b-300db9ab3d04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159462351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3159462351
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2145911185
Short name T57
Test name
Test status
Simulation time 1899345380 ps
CPU time 1.31 seconds
Started Jun 23 06:00:47 PM PDT 24
Finished Jun 23 06:00:49 PM PDT 24
Peak memory 205108 kb
Host smart-a2781580-15dc-4691-85f9-a9f0a57dbaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145911185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2145911185
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.600364665
Short name T38
Test name
Test status
Simulation time 4627260173 ps
CPU time 12.69 seconds
Started Jun 23 06:00:45 PM PDT 24
Finished Jun 23 06:00:57 PM PDT 24
Peak memory 205200 kb
Host smart-eb5d6cd0-0373-4524-a5ca-ee90e0534075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600364665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.600364665
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2978125688
Short name T31
Test name
Test status
Simulation time 11702873900 ps
CPU time 30.92 seconds
Started Jun 23 06:00:46 PM PDT 24
Finished Jun 23 06:01:17 PM PDT 24
Peak memory 205188 kb
Host smart-55c8104f-3372-42be-97a9-1925588964c5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978125688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2978125688
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3304825848
Short name T228
Test name
Test status
Simulation time 2439816248 ps
CPU time 4.13 seconds
Started Jun 23 06:00:46 PM PDT 24
Finished Jun 23 06:00:50 PM PDT 24
Peak memory 205192 kb
Host smart-7ae9efc7-4d53-466b-a7bf-cb4630a707c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304825848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3304825848
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2815544673
Short name T24
Test name
Test status
Simulation time 12415212150 ps
CPU time 9.6 seconds
Started Jun 23 06:00:47 PM PDT 24
Finished Jun 23 06:00:57 PM PDT 24
Peak memory 205148 kb
Host smart-3e9466b9-8e15-4b5d-994e-cfb0f20fe497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815544673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2815544673
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.777284658
Short name T240
Test name
Test status
Simulation time 6299670118 ps
CPU time 8.16 seconds
Started Jun 23 06:00:48 PM PDT 24
Finished Jun 23 06:00:56 PM PDT 24
Peak memory 205216 kb
Host smart-8111cdbb-a821-4ea4-a7b4-bbb66bd75522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777284658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.777284658
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3069659941
Short name T195
Test name
Test status
Simulation time 5643298452 ps
CPU time 2.77 seconds
Started Jun 23 06:00:49 PM PDT 24
Finished Jun 23 06:00:52 PM PDT 24
Peak memory 205140 kb
Host smart-34904fb5-cbf2-4411-90ac-401679a98d87
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3069659941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3069659941
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2064333878
Short name T220
Test name
Test status
Simulation time 3385987862 ps
CPU time 10.05 seconds
Started Jun 23 06:00:46 PM PDT 24
Finished Jun 23 06:00:57 PM PDT 24
Peak memory 205180 kb
Host smart-077457c2-cb40-4d40-b071-dbdd2fb1ee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064333878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2064333878
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2659334002
Short name T50
Test name
Test status
Simulation time 49675040 ps
CPU time 0.72 seconds
Started Jun 23 06:00:50 PM PDT 24
Finished Jun 23 06:00:51 PM PDT 24
Peak memory 204804 kb
Host smart-ef2521ab-4d17-4158-afc0-114c7fde93a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659334002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2659334002
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.4075004465
Short name T258
Test name
Test status
Simulation time 2350019401 ps
CPU time 3.74 seconds
Started Jun 23 06:00:51 PM PDT 24
Finished Jun 23 06:00:55 PM PDT 24
Peak memory 205164 kb
Host smart-47b7a872-d4d8-4ca4-b7db-e2553ed0a6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075004465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.4075004465
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2750698023
Short name T211
Test name
Test status
Simulation time 1378806589 ps
CPU time 3.04 seconds
Started Jun 23 06:00:56 PM PDT 24
Finished Jun 23 06:01:00 PM PDT 24
Peak memory 205092 kb
Host smart-1127b79e-6951-432d-b8a1-e580a39c3c3f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750698023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2750698023
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.512755637
Short name T213
Test name
Test status
Simulation time 7439496949 ps
CPU time 5.84 seconds
Started Jun 23 06:00:52 PM PDT 24
Finished Jun 23 06:00:58 PM PDT 24
Peak memory 205124 kb
Host smart-df07629b-5cd9-4daa-90be-dad690c5c145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512755637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.512755637
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3784241035
Short name T221
Test name
Test status
Simulation time 32684032 ps
CPU time 0.75 seconds
Started Jun 23 06:00:58 PM PDT 24
Finished Jun 23 06:00:59 PM PDT 24
Peak memory 204708 kb
Host smart-c208ca02-d2b4-452e-a623-95ba386f0bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784241035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3784241035
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.31910499
Short name T189
Test name
Test status
Simulation time 36112420153 ps
CPU time 26.85 seconds
Started Jun 23 06:00:53 PM PDT 24
Finished Jun 23 06:01:20 PM PDT 24
Peak memory 213348 kb
Host smart-9b35358d-2ec8-4a5e-b565-0613e84e8b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31910499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.31910499
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3332597970
Short name T214
Test name
Test status
Simulation time 2227515730 ps
CPU time 7.63 seconds
Started Jun 23 06:00:53 PM PDT 24
Finished Jun 23 06:01:01 PM PDT 24
Peak memory 205284 kb
Host smart-254e4cb1-ad81-4e2c-83a1-0a90e9fb636a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332597970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3332597970
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3315976390
Short name T235
Test name
Test status
Simulation time 2018536249 ps
CPU time 1.62 seconds
Started Jun 23 06:00:54 PM PDT 24
Finished Jun 23 06:00:56 PM PDT 24
Peak memory 205080 kb
Host smart-7b8556db-3075-41bc-9fa2-9429cdce7629
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3315976390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3315976390
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1155667803
Short name T245
Test name
Test status
Simulation time 2750785911 ps
CPU time 4.42 seconds
Started Jun 23 06:00:55 PM PDT 24
Finished Jun 23 06:00:59 PM PDT 24
Peak memory 205184 kb
Host smart-c591090c-92a6-49b0-93bf-74a1814e7750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155667803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1155667803
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3867245769
Short name T209
Test name
Test status
Simulation time 127459387 ps
CPU time 0.83 seconds
Started Jun 23 06:01:01 PM PDT 24
Finished Jun 23 06:01:03 PM PDT 24
Peak memory 204776 kb
Host smart-439def92-0a57-47dc-a69b-58ee123d5f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867245769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3867245769
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.311248376
Short name T23
Test name
Test status
Simulation time 2204843817 ps
CPU time 5.94 seconds
Started Jun 23 06:00:56 PM PDT 24
Finished Jun 23 06:01:02 PM PDT 24
Peak memory 205220 kb
Host smart-5c21409d-d7ca-4773-8f58-7a7a94580d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311248376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.311248376
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1741390928
Short name T216
Test name
Test status
Simulation time 6263778334 ps
CPU time 8.28 seconds
Started Jun 23 06:00:58 PM PDT 24
Finished Jun 23 06:01:06 PM PDT 24
Peak memory 205284 kb
Host smart-c0be5e66-b03c-45bc-b0f0-7cb681853a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741390928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1741390928
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3087200654
Short name T222
Test name
Test status
Simulation time 967217722 ps
CPU time 3.75 seconds
Started Jun 23 06:00:58 PM PDT 24
Finished Jun 23 06:01:02 PM PDT 24
Peak memory 205120 kb
Host smart-2dc524bc-e868-45b0-8081-10d21e740b38
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3087200654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3087200654
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3137951627
Short name T253
Test name
Test status
Simulation time 5395947257 ps
CPU time 3.47 seconds
Started Jun 23 06:00:58 PM PDT 24
Finished Jun 23 06:01:02 PM PDT 24
Peak memory 205156 kb
Host smart-df373e6d-166e-4896-b093-6d21327b8dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137951627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3137951627
Directory /workspace/9.rv_dm_sba_tl_access/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%