Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	209489	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	575629	1		T5	64		T8	1		T9	9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	493241	1		T5	32		T9	6		T30	6
values[0x0]	143960	1		T5	36		T8	5		T9	8
values[0x1]	147917	1		T5	47		T8	3		T9	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	161099	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	624019	1		T5	69		T8	2		T9	12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3610	1		T34	1		T44	10		T49	14
valid_sources[0x01]	2892	1		T14	1		T126	1		T44	8
valid_sources[0x02]	3115	1		T28	2		T114	2		T19	2
valid_sources[0x03]	3286	1		T6	2		T114	2		T44	1
valid_sources[0x04]	3050	1		T28	1		T127	1		T44	3
valid_sources[0x05]	3014	1		T30	1		T44	3		T76	15
valid_sources[0x06]	2953	1		T28	1		T128	14		T44	4
valid_sources[0x07]	2823	1		T5	1		T44	2		T49	40
valid_sources[0x08]	3006	1		T9	1		T68	1		T29	6
valid_sources[0x09]	2899	1		T44	6		T49	5		T76	24
valid_sources[0x0a]	3443	1		T23	3		T34	1		T127	2
valid_sources[0x0b]	2967	1		T5	1		T28	5		T14	1
valid_sources[0x0c]	3120	1		T5	2		T44	5		T49	20
valid_sources[0x0d]	3003	1		T5	3		T28	1		T32	3
valid_sources[0x0e]	3114	1		T6	1		T28	1		T14	1
valid_sources[0x0f]	2985	1		T5	2		T18	2		T44	2
valid_sources[0x10]	2914	1		T28	1		T44	3		T76	32
valid_sources[0x11]	3151	1		T5	1		T23	4		T29	1
valid_sources[0x12]	2952	1		T5	3		T44	7		T49	42
valid_sources[0x13]	2915	1		T127	1		T44	4		T49	21
valid_sources[0x14]	2965	1		T44	7		T49	3		T76	17
valid_sources[0x15]	3110	1		T127	1		T44	3		T49	24
valid_sources[0x16]	2943	1		T14	1		T44	7		T76	17
valid_sources[0x17]	3105	1		T6	2		T44	8		T76	20
valid_sources[0x18]	3185	1		T28	1		T68	1		T44	12
valid_sources[0x19]	2787	1		T14	1		T44	9		T49	6
valid_sources[0x1a]	3461	1		T44	4		T49	6		T76	46
valid_sources[0x1b]	3154	1		T127	1		T44	6		T49	24
valid_sources[0x1c]	3584	1		T28	1		T44	10		T76	34
valid_sources[0x1d]	3096	1		T127	2		T44	7		T49	30
valid_sources[0x1e]	3499	1		T30	2		T22	1		T129	2
valid_sources[0x1f]	3398	1		T127	1		T44	1		T49	24
valid_sources[0x20]	3105	1		T6	2		T28	2		T29	3
valid_sources[0x21]	3431	1		T31	1		T127	1		T44	8
valid_sources[0x22]	2692	1		T5	1		T30	1		T44	3
valid_sources[0x23]	3216	1		T5	1		T28	2		T44	5
valid_sources[0x24]	3863	1		T5	2		T28	1		T114	1
valid_sources[0x25]	2781	1		T5	2		T7	107		T28	1
valid_sources[0x26]	3194	1		T6	1		T114	1		T127	1
valid_sources[0x27]	2992	1		T9	1		T44	5		T49	21
valid_sources[0x28]	3365	1		T127	1		T44	6		T76	21
valid_sources[0x29]	3053	1		T6	1		T127	1		T44	12
valid_sources[0x2a]	3152	1		T5	1		T29	2		T130	3
valid_sources[0x2b]	2909	1		T28	1		T29	2		T44	5
valid_sources[0x2c]	2971	1		T28	1		T33	2		T44	6
valid_sources[0x2d]	2847	1		T114	2		T44	8		T49	3
valid_sources[0x2e]	2865	1		T9	1		T28	2		T114	1
valid_sources[0x2f]	3026	1		T5	1		T44	17		T76	21
valid_sources[0x30]	2715	1		T68	1		T44	7		T76	27
valid_sources[0x31]	3139	1		T34	3		T14	2		T127	1
valid_sources[0x32]	2847	1		T131	3		T44	3		T49	1
valid_sources[0x33]	3121	1		T44	8		T76	20		T45	8
valid_sources[0x34]	3007	1		T5	2		T9	1		T39	3
valid_sources[0x35]	2828	1		T29	1		T12	1		T132	3
valid_sources[0x36]	2860	1		T22	3		T35	89		T127	1
valid_sources[0x37]	3350	1		T28	1		T19	1		T44	9
valid_sources[0x38]	2683	1		T6	4		T28	2		T68	1
valid_sources[0x39]	3031	1		T29	2		T39	1		T44	5
valid_sources[0x3a]	3121	1		T5	1		T44	3		T76	24
valid_sources[0x3b]	3059	1		T14	2		T44	11		T76	33
valid_sources[0x3c]	3002	1		T14	1		T44	6		T49	36
valid_sources[0x3d]	3064	1		T17	6		T44	5		T49	13
valid_sources[0x3e]	3463	1		T6	2		T44	6		T49	13
valid_sources[0x3f]	2631	1		T5	1		T30	1		T28	1
valid_sources[0x40]	2850	1		T5	2		T14	1		T127	1
valid_sources[0x41]	3130	1		T29	2		T44	1		T76	15
valid_sources[0x42]	3235	1		T28	1		T14	1		T32	3
valid_sources[0x43]	3203	1		T6	3		T127	1		T44	10
valid_sources[0x44]	3103	1		T23	4		T28	1		T114	1
valid_sources[0x45]	2836	1		T114	1		T44	6		T49	27
valid_sources[0x46]	3228	1		T44	10		T76	22		T77	7
valid_sources[0x47]	2835	1		T5	2		T133	5		T44	2
valid_sources[0x48]	4236	1		T114	1		T14	1		T44	18
valid_sources[0x49]	3308	1		T68	1		T44	14		T76	23
valid_sources[0x4a]	3190	1		T44	7		T49	11		T76	25
valid_sources[0x4b]	2621	1		T5	4		T6	1		T28	1
valid_sources[0x4c]	2655	1		T28	1		T114	1		T14	1
valid_sources[0x4d]	2974	1		T5	1		T29	2		T44	9
valid_sources[0x4e]	3379	1		T5	1		T28	3		T44	7
valid_sources[0x4f]	3403	1		T44	9		T49	11		T76	36
valid_sources[0x50]	3180	1		T44	10		T76	31		T45	11
valid_sources[0x51]	3316	1		T9	1		T22	12		T28	1
valid_sources[0x52]	2692	1		T5	2		T14	1		T44	6
valid_sources[0x53]	3216	1		T44	6		T49	34		T76	19
valid_sources[0x54]	2907	1		T5	2		T8	8		T6	1
valid_sources[0x55]	4118	1		T5	5		T34	1		T133	21
valid_sources[0x56]	3039	1		T44	2		T76	19		T77	1
valid_sources[0x57]	2573	1		T29	1		T34	1		T127	1
valid_sources[0x58]	2743	1		T44	10		T49	25		T76	33
valid_sources[0x59]	3003	1		T29	1		T114	1		T44	17
valid_sources[0x5a]	3036	1		T5	4		T29	2		T44	4
valid_sources[0x5b]	3078	1		T9	1		T44	6		T49	16
valid_sources[0x5c]	2761	1		T9	1		T28	1		T44	6
valid_sources[0x5d]	3177	1		T29	1		T114	1		T15	52
valid_sources[0x5e]	3038	1		T6	1		T34	3		T127	1
valid_sources[0x5f]	2819	1		T14	1		T127	1		T44	4
valid_sources[0x60]	2837	1		T6	1		T28	1		T132	2
valid_sources[0x61]	2692	1		T5	1		T44	3		T49	41
valid_sources[0x62]	2842	1		T30	2		T14	1		T132	2
valid_sources[0x63]	3312	1		T5	1		T30	3		T28	2
valid_sources[0x64]	2957	1		T44	3		T76	27		T77	3
valid_sources[0x65]	2957	1		T127	2		T44	9		T49	2
valid_sources[0x66]	3303	1		T44	4		T49	4		T76	17
valid_sources[0x67]	3508	1		T5	1		T29	1		T44	15
valid_sources[0x68]	3143	1		T34	1		T44	6		T76	19
valid_sources[0x69]	3343	1		T22	13		T44	8		T49	6
valid_sources[0x6a]	2828	1		T5	1		T28	2		T132	4
valid_sources[0x6b]	2636	1		T5	2		T9	2		T30	1
valid_sources[0x6c]	2976	1		T44	11		T76	21		T77	31
valid_sources[0x6d]	3379	1		T127	1		T44	8		T49	11
valid_sources[0x6e]	3835	1		T6	2		T44	14		T49	14
valid_sources[0x6f]	2965	1		T22	1		T36	9		T34	1
valid_sources[0x70]	3153	1		T5	1		T29	1		T34	3
valid_sources[0x71]	2758	1		T30	1		T132	1		T44	9
valid_sources[0x72]	3231	1		T132	1		T44	4		T76	37
valid_sources[0x73]	3275	1		T22	1		T23	2		T44	9
valid_sources[0x74]	3131	1		T28	1		T44	11		T76	17
valid_sources[0x75]	2902	1		T29	1		T114	1		T14	1
valid_sources[0x76]	2890	1		T9	1		T29	2		T34	2
valid_sources[0x77]	2876	1		T6	1		T29	1		T44	6
valid_sources[0x78]	3273	1		T9	1		T22	1		T28	1
valid_sources[0x79]	2658	1		T5	1		T28	1		T14	1
valid_sources[0x7a]	3684	1		T68	1		T29	1		T34	1
valid_sources[0x7b]	3025	1		T44	1		T49	26		T76	15
valid_sources[0x7c]	2767	1		T14	1		T132	1		T76	18
valid_sources[0x7d]	3529	1		T44	4		T49	6		T76	18
valid_sources[0x7e]	3070	1		T5	2		T6	2		T14	1
valid_sources[0x7f]	3261	1		T5	2		T6	1		T22	1
valid_sources[0x80]	2728	1		T37	2		T44	5		T49	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

291274

1

T5

19

T9

4

T30

1

values[0x0]

all_enables

biggest_size

142168

1

T5

23

T8

1

T9

5

values[0x1]

all_enables

biggest_size

142187

1

T5

22

T6

5

T30

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5501	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	14286	1		T2	1		T24	1		T25	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9242	1		T48	6		T44	97		T49	18
values[0x0]	5160	1		T2	3		T24	7		T25	2
values[0x1]	5385	1		T2	6		T24	6		T25	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4248	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	15539	1		T2	1		T24	3		T25	3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	75	1		T44	1		T78	11		T70	3
valid_sources[0x01]	45	1		T2	3		T24	1		T44	2
valid_sources[0x02]	57	1		T44	5		T47	1		T78	1
valid_sources[0x03]	66	1		T44	3		T78	1		T70	3
valid_sources[0x04]	62	1		T24	2		T134	1		T44	2
valid_sources[0x05]	80	1		T135	19		T136	3		T44	1
valid_sources[0x06]	224	1		T64	9		T44	1		T49	1
valid_sources[0x07]	55	1		T137	1		T44	1		T49	1
valid_sources[0x08]	121	1		T24	2		T45	1		T78	1
valid_sources[0x09]	76	1		T2	1		T24	1		T138	1
valid_sources[0x0a]	74	1		T139	2		T44	2		T49	2
valid_sources[0x0b]	89	1		T140	3		T44	3		T49	1
valid_sources[0x0c]	53	1		T112	1		T44	4		T78	5
valid_sources[0x0d]	65	1		T141	1		T142	1		T44	2
valid_sources[0x0e]	53	1		T139	1		T72	1		T75	1
valid_sources[0x0f]	94	1		T44	2		T76	1		T46	9
valid_sources[0x10]	55	1		T143	1		T44	1		T78	3
valid_sources[0x11]	64	1		T78	4		T70	2		T72	1
valid_sources[0x12]	70	1		T78	1		T80	1		T70	1
valid_sources[0x13]	82	1		T144	2		T44	1		T78	1
valid_sources[0x14]	66	1		T44	1		T47	1		T46	7
valid_sources[0x15]	92	1		T145	1		T44	1		T47	1
valid_sources[0x16]	85	1		T25	2		T78	5		T70	1
valid_sources[0x17]	75	1		T65	3		T44	1		T46	7
valid_sources[0x18]	57	1		T44	2		T49	1		T47	1
valid_sources[0x19]	87	1		T49	1		T45	2		T78	2
valid_sources[0x1a]	73	1		T141	1		T134	2		T146	1
valid_sources[0x1b]	76	1		T140	1		T47	1		T78	4
valid_sources[0x1c]	63	1		T139	1		T76	1		T45	2
valid_sources[0x1d]	71	1		T144	1		T44	3		T76	2
valid_sources[0x1e]	80	1		T50	1		T78	4		T70	2
valid_sources[0x1f]	77	1		T44	3		T47	1		T78	9
valid_sources[0x20]	74	1		T44	1		T94	1		T74	2
valid_sources[0x21]	93	1		T44	4		T45	4		T78	6
valid_sources[0x22]	61	1		T147	1		T148	7		T44	1
valid_sources[0x23]	76	1		T149	1		T150	6		T44	1
valid_sources[0x24]	67	1		T44	1		T76	1		T78	1
valid_sources[0x25]	55	1		T44	2		T78	3		T70	4
valid_sources[0x26]	52	1		T47	1		T78	1		T70	4
valid_sources[0x27]	52	1		T44	2		T78	4		T69	1
valid_sources[0x28]	70	1		T139	1		T151	5		T152	2
valid_sources[0x29]	110	1		T149	1		T44	2		T78	4
valid_sources[0x2a]	187	1		T153	2		T143	2		T78	2
valid_sources[0x2b]	54	1		T154	4		T137	1		T76	2
valid_sources[0x2c]	78	1		T155	3		T44	2		T76	1
valid_sources[0x2d]	87	1		T137	1		T44	1		T45	2
valid_sources[0x2e]	47	1		T143	1		T156	1		T44	1
valid_sources[0x2f]	58	1		T47	1		T78	2		T73	1
valid_sources[0x30]	73	1		T157	2		T134	1		T152	4
valid_sources[0x31]	78	1		T48	1		T44	1		T49	2
valid_sources[0x32]	118	1		T147	1		T138	3		T78	1
valid_sources[0x33]	59	1		T147	2		T44	1		T76	1
valid_sources[0x34]	55	1		T156	2		T44	1		T78	4
valid_sources[0x35]	107	1		T158	1		T154	3		T159	2
valid_sources[0x36]	92	1		T66	18		T138	2		T44	2
valid_sources[0x37]	61	1		T78	2		T70	2		T74	1
valid_sources[0x38]	77	1		T154	2		T44	1		T49	1
valid_sources[0x39]	98	1		T139	1		T44	1		T78	5
valid_sources[0x3a]	64	1		T160	1		T152	2		T78	3
valid_sources[0x3b]	73	1		T44	1		T78	1		T70	1
valid_sources[0x3c]	105	1		T44	1		T76	1		T69	3
valid_sources[0x3d]	88	1		T139	1		T143	1		T44	1
valid_sources[0x3e]	56	1		T153	3		T76	1		T78	2
valid_sources[0x3f]	98	1		T139	1		T44	2		T78	3
valid_sources[0x40]	76	1		T134	1		T76	1		T45	5
valid_sources[0x41]	68	1		T147	1		T48	1		T44	1
valid_sources[0x42]	101	1		T50	1		T44	1		T78	1
valid_sources[0x43]	77	1		T149	1		T141	1		T44	1
valid_sources[0x44]	78	1		T44	2		T78	4		T70	2
valid_sources[0x45]	58	1		T156	1		T44	5		T78	7
valid_sources[0x46]	70	1		T44	7		T49	1		T46	1
valid_sources[0x47]	113	1		T54	1		T44	1		T76	2
valid_sources[0x48]	62	1		T145	1		T44	4		T78	1
valid_sources[0x49]	72	1		T47	1		T69	1		T70	2
valid_sources[0x4a]	70	1		T44	6		T70	1		T72	1
valid_sources[0x4b]	62	1		T145	1		T156	1		T78	2
valid_sources[0x4c]	65	1		T44	1		T78	2		T70	3
valid_sources[0x4d]	78	1		T112	1		T48	1		T44	2
valid_sources[0x4e]	55	1		T44	1		T78	2		T80	1
valid_sources[0x4f]	73	1		T134	1		T44	4		T46	1
valid_sources[0x50]	62	1		T147	1		T134	1		T155	1
valid_sources[0x51]	65	1		T44	2		T78	4		T70	2
valid_sources[0x52]	68	1		T78	2		T71	1		T72	2
valid_sources[0x53]	76	1		T161	8		T145	1		T162	2
valid_sources[0x54]	74	1		T152	4		T44	1		T78	1
valid_sources[0x55]	62	1		T142	2		T44	4		T78	4
valid_sources[0x56]	63	1		T112	3		T44	1		T49	1
valid_sources[0x57]	75	1		T45	7		T46	7		T70	1
valid_sources[0x58]	87	1		T44	2		T70	1		T71	1
valid_sources[0x59]	73	1		T44	4		T78	3		T69	1
valid_sources[0x5a]	85	1		T44	2		T78	2		T72	2
valid_sources[0x5b]	59	1		T24	2		T147	1		T44	1
valid_sources[0x5c]	66	1		T137	1		T44	2		T76	3
valid_sources[0x5d]	52	1		T44	1		T76	1		T45	1
valid_sources[0x5e]	78	1		T48	1		T76	4		T47	1
valid_sources[0x5f]	60	1		T76	1		T45	1		T78	4
valid_sources[0x60]	110	1		T2	1		T54	1		T163	7
valid_sources[0x61]	61	1		T44	1		T45	2		T46	3
valid_sources[0x62]	64	1		T44	1		T70	1		T71	2
valid_sources[0x63]	50	1		T153	9		T137	1		T44	1
valid_sources[0x64]	81	1		T137	1		T49	1		T78	2
valid_sources[0x65]	149	1		T153	2		T44	2		T45	3
valid_sources[0x66]	91	1		T54	1		T44	3		T49	1
valid_sources[0x67]	76	1		T156	1		T44	2		T76	1
valid_sources[0x68]	57	1		T44	2		T47	1		T78	1
valid_sources[0x69]	85	1		T156	1		T48	1		T44	3
valid_sources[0x6a]	53	1		T78	1		T70	2		T72	1
valid_sources[0x6b]	58	1		T149	1		T44	2		T70	3
valid_sources[0x6c]	105	1		T164	14		T45	1		T78	2
valid_sources[0x6d]	66	1		T59	2		T44	4		T78	1
valid_sources[0x6e]	54	1		T44	3		T70	1		T74	1
valid_sources[0x6f]	68	1		T165	3		T44	2		T47	1
valid_sources[0x70]	66	1		T134	1		T158	2		T44	1
valid_sources[0x71]	76	1		T44	1		T47	1		T78	1
valid_sources[0x72]	49	1		T47	1		T70	2		T82	1
valid_sources[0x73]	78	1		T140	1		T44	4		T78	2
valid_sources[0x74]	90	1		T113	11		T44	1		T49	1
valid_sources[0x75]	69	1		T76	1		T78	2		T70	2
valid_sources[0x76]	72	1		T149	1		T45	4		T78	2
valid_sources[0x77]	65	1		T157	2		T142	3		T78	1
valid_sources[0x78]	45	1		T143	1		T44	2		T78	2
valid_sources[0x79]	71	1		T44	2		T78	2		T69	1
valid_sources[0x7a]	55	1		T139	1		T44	1		T45	1
valid_sources[0x7b]	62	1		T153	2		T156	1		T44	3
valid_sources[0x7c]	68	1		T137	1		T78	3		T70	1
valid_sources[0x7d]	73	1		T139	3		T44	1		T47	1
valid_sources[0x7e]	100	1		T139	3		T76	2		T78	1
valid_sources[0x7f]	71	1		T54	1		T44	3		T76	4
valid_sources[0x80]	111	1		T44	1		T78	4		T70	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5737

1

T48

2

T44

89

T49

18

values[0x0]

all_enables

biggest_size

4387

1

T2

1

T25

1

T64

1

values[0x1]

all_enables

biggest_size

4162

1

T24

1

T25

2

T56

1