Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	240359	1		T5	51		T8	7		T9	8
full_word	576929	1		T5	64		T8	1		T9	9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	817008	1		T5	115		T8	8		T9	17
auto[TlIntgErrCmd]	96	1		T46	7		T72	10		T74	8
auto[TlIntgErrData]	93	1		T46	9		T72	4		T74	8
auto[TlIntgErrBoth]	91	1		T46	4		T72	6		T74	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	494703	1		T5	32		T9	6		T30	6
auto[1]	322585	1		T5	83		T8	8		T9	11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	203153	1		T5	13		T9	2		T30	5
auto[TlIntgErrNone]	partial	auto[1]	36952	1		T5	38		T8	7		T9	6
auto[TlIntgErrNone]	full_word	auto[0]	291425	1		T5	19		T9	4		T30	1
auto[TlIntgErrNone]	full_word	auto[1]	285478	1		T5	45		T8	1		T9	5
auto[TlIntgErrCmd]	partial	auto[0]	40	1		T46	4		T72	5		T74	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T46	3		T72	3		T74	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T72	2		T121	1		T122	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T74	1		T120	1		T118	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T46	5		T72	2		T74	1
auto[TlIntgErrData]	partial	auto[1]	42	1		T46	3		T72	2		T74	6
auto[TlIntgErrData]	full_word	auto[0]	4	1		T120	1		T121	2		T123	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T46	1		T74	1		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T46	2		T72	3		T84	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T46	2		T72	3		T74	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T118	1		T124	1		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T121	1		T125	1		T122	1