Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.85	96.97	55.32	89.47		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	123949959	11089	0	0
late_debug_enable_rd_A	123949959	4358	0	0
late_debug_enable_regwen_rd_A	123949959	5097	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123949959	11089	0	0
T44	318808	173	0	0
T45	146983	29	0	0
T46	118409	7	0	0
T47	12653	244	0	0
T69	8533	37	0	0
T70	15502	841	0	0
T71	229006	26	0	0
T72	167393	4	0	0
T73	15487	406	0	0
T74	160348	4	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123949959	4358	0	0
T47	12653	22	0	0
T69	8533	31	0	0
T71	229006	24	0	0
T72	167393	65	0	0
T77	14345	6	0	0
T79	10022	8	0	0
T93	23305	8	0	0
T95	38324	10	0	0
T96	55100	17	0	0
T109	49923	34	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123949959	5097	0	0
T47	12653	45	0	0
T69	8533	13	0	0
T71	229006	44	0	0
T72	167393	123	0	0
T77	14345	14	0	0
T79	10022	5	0	0
T80	12000	3	0	0
T93	23305	7	0	0
T95	38324	6	0	0
T109	49923	35	0	0