Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
8622271 |
8621067 |
0 |
0 |
selKnown1 |
57721903 |
57720699 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8622271 |
8621067 |
0 |
0 |
T1 |
53379 |
53375 |
0 |
0 |
T2 |
444 |
440 |
0 |
0 |
T3 |
28798 |
28794 |
0 |
0 |
T4 |
31147 |
31143 |
0 |
0 |
T5 |
107788 |
107784 |
0 |
0 |
T6 |
0 |
26 |
0 |
0 |
T7 |
0 |
15 |
0 |
0 |
T8 |
6160 |
6156 |
0 |
0 |
T9 |
0 |
26 |
0 |
0 |
T10 |
9801 |
9797 |
0 |
0 |
T11 |
25593 |
25589 |
0 |
0 |
T20 |
0 |
18 |
0 |
0 |
T21 |
0 |
4 |
0 |
0 |
T22 |
0 |
11 |
0 |
0 |
T24 |
438 |
434 |
0 |
0 |
T25 |
1486 |
1482 |
0 |
0 |
T43 |
0 |
14 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
57721903 |
57720699 |
0 |
0 |
T1 |
761374 |
761370 |
0 |
0 |
T2 |
4155 |
4151 |
0 |
0 |
T3 |
252786 |
252782 |
0 |
0 |
T4 |
145011 |
145007 |
0 |
0 |
T5 |
230944 |
230941 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T7 |
0 |
8 |
0 |
0 |
T8 |
72897 |
72893 |
0 |
0 |
T9 |
0 |
12 |
0 |
0 |
T10 |
106862 |
106858 |
0 |
0 |
T11 |
92236 |
92232 |
0 |
0 |
T20 |
0 |
18 |
0 |
0 |
T21 |
0 |
4 |
0 |
0 |
T22 |
0 |
4 |
0 |
0 |
T24 |
2728 |
2724 |
0 |
0 |
T25 |
2026 |
2022 |
0 |
0 |
T43 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2805966 |
2805770 |
0 |
0 |
selKnown1 |
51906026 |
51905830 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2805966 |
2805770 |
0 |
0 |
T1 |
26681 |
26680 |
0 |
0 |
T2 |
221 |
220 |
0 |
0 |
T3 |
14398 |
14397 |
0 |
0 |
T4 |
15568 |
15567 |
0 |
0 |
T5 |
53887 |
53886 |
0 |
0 |
T8 |
3079 |
3078 |
0 |
0 |
T10 |
4899 |
4898 |
0 |
0 |
T11 |
12795 |
12794 |
0 |
0 |
T24 |
218 |
217 |
0 |
0 |
T25 |
742 |
741 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
51906026 |
51905830 |
0 |
0 |
T1 |
734677 |
734676 |
0 |
0 |
T2 |
3932 |
3931 |
0 |
0 |
T3 |
238386 |
238385 |
0 |
0 |
T4 |
129433 |
129432 |
0 |
0 |
T5 |
177043 |
177043 |
0 |
0 |
T8 |
69816 |
69815 |
0 |
0 |
T10 |
101961 |
101960 |
0 |
0 |
T11 |
79439 |
79438 |
0 |
0 |
T24 |
2508 |
2507 |
0 |
0 |
T25 |
1282 |
1281 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
599 |
403 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T6 |
0 |
13 |
0 |
0 |
T7 |
0 |
4 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
0 |
13 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T43 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
531 |
335 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
0 |
4 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
0 |
6 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T43 |
0 |
7 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
5814178 |
5813772 |
0 |
0 |
selKnown1 |
5813985 |
5813579 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5814178 |
5813772 |
0 |
0 |
T1 |
26682 |
26681 |
0 |
0 |
T2 |
221 |
220 |
0 |
0 |
T3 |
14398 |
14397 |
0 |
0 |
T4 |
15569 |
15568 |
0 |
0 |
T5 |
53887 |
53886 |
0 |
0 |
T8 |
3079 |
3078 |
0 |
0 |
T10 |
4900 |
4899 |
0 |
0 |
T11 |
12796 |
12795 |
0 |
0 |
T24 |
218 |
217 |
0 |
0 |
T25 |
742 |
741 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5813985 |
5813579 |
0 |
0 |
T1 |
26681 |
26680 |
0 |
0 |
T2 |
221 |
220 |
0 |
0 |
T3 |
14398 |
14397 |
0 |
0 |
T4 |
15568 |
15567 |
0 |
0 |
T5 |
53887 |
53886 |
0 |
0 |
T8 |
3079 |
3078 |
0 |
0 |
T10 |
4899 |
4898 |
0 |
0 |
T11 |
12795 |
12794 |
0 |
0 |
T24 |
218 |
217 |
0 |
0 |
T25 |
742 |
741 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1528 |
1122 |
0 |
0 |
selKnown1 |
1361 |
955 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1528 |
1122 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T6 |
0 |
13 |
0 |
0 |
T7 |
0 |
11 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
0 |
13 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T22 |
0 |
9 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T43 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1361 |
955 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
0 |
4 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
0 |
6 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T20 |
0 |
9 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T43 |
0 |
7 |
0 |
0 |