Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 225551 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 600212 1 T1 2 T6 80 T2 5



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 522362 1 T6 80 T2 2 T27 18
values[0x0] 149415 1 T1 3 T2 4 T3 8
values[0x1] 153986 1 T1 5 T2 6 T3 9



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 171920 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 653843 1 T1 3 T6 80 T2 5



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3324 1 T2 1 T8 1 T62 5
valid_sources[0x01] 3561 1 T63 3 T64 28 T69 1
valid_sources[0x02] 3036 1 T135 2 T64 18 T69 4
valid_sources[0x03] 3013 1 T2 1 T15 1 T62 8
valid_sources[0x04] 3450 1 T5 1 T47 1 T62 29
valid_sources[0x05] 3254 1 T18 1 T136 1 T137 1
valid_sources[0x06] 2928 1 T11 1 T62 15 T63 1
valid_sources[0x07] 2740 1 T3 1 T11 1 T62 6
valid_sources[0x08] 3117 1 T47 2 T48 1 T50 1
valid_sources[0x09] 2971 1 T47 2 T15 1 T62 14
valid_sources[0x0a] 3214 1 T138 1 T139 1 T62 1
valid_sources[0x0b] 3307 1 T47 1 T140 1 T63 6
valid_sources[0x0c] 2685 1 T53 1 T62 16 T63 5
valid_sources[0x0d] 2890 1 T5 1 T8 1 T141 21
valid_sources[0x0e] 3285 1 T137 1 T50 2 T62 2
valid_sources[0x0f] 3122 1 T18 1 T62 5 T63 3
valid_sources[0x10] 3467 1 T21 11 T47 1 T137 1
valid_sources[0x11] 3518 1 T48 1 T136 2 T121 1
valid_sources[0x12] 3383 1 T63 1 T64 18 T69 1
valid_sources[0x13] 3260 1 T10 1 T11 1 T47 1
valid_sources[0x14] 3000 1 T5 1 T15 1 T62 14
valid_sources[0x15] 3412 1 T142 2 T47 1 T8 1
valid_sources[0x16] 3177 1 T62 8 T63 5 T64 24
valid_sources[0x17] 3018 1 T47 1 T137 1 T140 1
valid_sources[0x18] 2779 1 T136 1 T22 1 T138 1
valid_sources[0x19] 2862 1 T62 11 T63 6 T64 24
valid_sources[0x1a] 3006 1 T11 1 T48 1 T143 35
valid_sources[0x1b] 3098 1 T11 1 T138 1 T62 7
valid_sources[0x1c] 3581 1 T5 2 T47 1 T48 1
valid_sources[0x1d] 4197 1 T5 2 T8 1 T62 7
valid_sources[0x1e] 3086 1 T48 1 T144 1 T22 1
valid_sources[0x1f] 3191 1 T3 1 T138 1 T62 20
valid_sources[0x20] 3189 1 T145 1 T146 31 T62 11
valid_sources[0x21] 2815 1 T147 4 T137 1 T63 5
valid_sources[0x22] 2911 1 T30 1 T22 1 T62 3
valid_sources[0x23] 3057 1 T47 2 T121 3 T148 2
valid_sources[0x24] 2701 1 T5 1 T47 1 T53 1
valid_sources[0x25] 3163 1 T47 1 T62 2 T63 3
valid_sources[0x26] 3278 1 T47 1 T137 1 T15 1
valid_sources[0x27] 2954 1 T81 1 T149 1 T53 1
valid_sources[0x28] 3015 1 T81 1 T121 1 T8 1
valid_sources[0x29] 2924 1 T63 5 T64 18 T69 8
valid_sources[0x2a] 3451 1 T63 2 T64 19 T82 23
valid_sources[0x2b] 3294 1 T81 1 T51 2 T145 2
valid_sources[0x2c] 3077 1 T53 1 T139 3 T15 3
valid_sources[0x2d] 3057 1 T3 1 T144 1 T138 1
valid_sources[0x2e] 3463 1 T5 1 T10 1 T11 1
valid_sources[0x2f] 3032 1 T144 1 T8 1 T62 17
valid_sources[0x30] 2952 1 T121 1 T150 1 T62 1
valid_sources[0x31] 3038 1 T11 1 T151 2 T62 3
valid_sources[0x32] 3804 1 T62 8 T63 5 T64 29
valid_sources[0x33] 2982 1 T63 1 T64 18 T69 4
valid_sources[0x34] 3067 1 T11 1 T17 6 T152 1
valid_sources[0x35] 3582 1 T62 31 T63 1 T64 28
valid_sources[0x36] 3189 1 T138 1 T153 2 T62 6
valid_sources[0x37] 3811 1 T11 1 T62 4 T63 6
valid_sources[0x38] 3126 1 T10 1 T47 1 T8 1
valid_sources[0x39] 2939 1 T47 1 T62 17 T64 21
valid_sources[0x3a] 3096 1 T7 31 T63 7 T64 22
valid_sources[0x3b] 3162 1 T51 18 T62 17 T63 4
valid_sources[0x3c] 3170 1 T140 1 T62 4 T63 2
valid_sources[0x3d] 2900 1 T48 1 T23 1 T62 2
valid_sources[0x3e] 2932 1 T11 1 T62 12 T63 6
valid_sources[0x3f] 3032 1 T51 6 T138 2 T154 2
valid_sources[0x40] 3062 1 T145 1 T121 2 T63 7
valid_sources[0x41] 3180 1 T10 2 T155 1 T121 1
valid_sources[0x42] 2796 1 T63 5 T64 20 T69 2
valid_sources[0x43] 3857 1 T139 2 T62 24 T63 3
valid_sources[0x44] 3167 1 T3 1 T10 4 T62 16
valid_sources[0x45] 3591 1 T47 1 T62 11 T63 14
valid_sources[0x46] 3156 1 T51 6 T47 1 T24 2
valid_sources[0x47] 3147 1 T8 1 T15 2 T62 6
valid_sources[0x48] 2722 1 T3 1 T156 2 T62 12
valid_sources[0x49] 3615 1 T9 3 T139 3 T62 1
valid_sources[0x4a] 3330 1 T31 24 T9 1 T53 1
valid_sources[0x4b] 3312 1 T35 1 T121 1 T24 1
valid_sources[0x4c] 3157 1 T10 2 T142 1 T47 1
valid_sources[0x4d] 3077 1 T34 1 T145 1 T62 1
valid_sources[0x4e] 3489 1 T62 4 T63 5 T64 18
valid_sources[0x4f] 3100 1 T47 1 T145 1 T149 1
valid_sources[0x50] 4088 1 T8 1 T157 1 T64 31
valid_sources[0x51] 3392 1 T5 1 T62 26 T63 3
valid_sources[0x52] 3174 1 T63 5 T64 18 T69 5
valid_sources[0x53] 3349 1 T158 1 T140 2 T62 1
valid_sources[0x54] 2925 1 T53 1 T140 1 T62 11
valid_sources[0x55] 3123 1 T150 1 T64 16 T69 3
valid_sources[0x56] 3134 1 T140 1 T62 13 T63 4
valid_sources[0x57] 3754 1 T47 2 T22 1 T159 1
valid_sources[0x58] 3290 1 T47 1 T48 1 T137 1
valid_sources[0x59] 3699 1 T47 1 T62 13 T63 1
valid_sources[0x5a] 2975 1 T10 3 T11 1 T53 1
valid_sources[0x5b] 3439 1 T15 2 T63 1 T64 23
valid_sources[0x5c] 3039 1 T137 1 T62 1 T63 2
valid_sources[0x5d] 3413 1 T24 1 T62 11 T63 14
valid_sources[0x5e] 3246 1 T2 3 T30 2 T47 1
valid_sources[0x5f] 3425 1 T24 3 T62 7 T63 3
valid_sources[0x60] 3213 1 T144 1 T63 1 T64 18
valid_sources[0x61] 2999 1 T5 1 T121 2 T8 1
valid_sources[0x62] 2967 1 T24 5 T16 51 T62 3
valid_sources[0x63] 2778 1 T62 4 T64 20 T69 2
valid_sources[0x64] 2752 1 T145 1 T8 1 T139 2
valid_sources[0x65] 2844 1 T53 1 T137 1 T62 1
valid_sources[0x66] 3136 1 T19 3 T5 1 T81 1
valid_sources[0x67] 4028 1 T47 1 T23 3 T150 1
valid_sources[0x68] 3427 1 T47 1 T9 1 T62 9
valid_sources[0x69] 3964 1 T52 16 T62 4 T63 2
valid_sources[0x6a] 3549 1 T152 1 T151 4 T63 2
valid_sources[0x6b] 2986 1 T47 1 T62 9 T63 3
valid_sources[0x6c] 3702 1 T11 1 T53 1 T151 2
valid_sources[0x6d] 3423 1 T10 2 T47 1 T53 1
valid_sources[0x6e] 2870 1 T62 18 T63 1 T64 19
valid_sources[0x6f] 3372 1 T121 1 T55 9 T53 1
valid_sources[0x70] 3450 1 T136 4 T137 1 T62 7
valid_sources[0x71] 3144 1 T144 1 T121 2 T63 5
valid_sources[0x72] 3177 1 T10 3 T8 1 T137 1
valid_sources[0x73] 2960 1 T62 3 T63 1 T64 21
valid_sources[0x74] 2791 1 T47 2 T144 1 T139 1
valid_sources[0x75] 3670 1 T63 1 T64 25 T82 38
valid_sources[0x76] 2821 1 T139 2 T137 1 T62 8
valid_sources[0x77] 3323 1 T10 2 T137 1 T62 9
valid_sources[0x78] 2936 1 T49 11 T8 1 T62 7
valid_sources[0x79] 2779 1 T47 1 T138 1 T153 1
valid_sources[0x7a] 3397 1 T10 1 T11 1 T47 1
valid_sources[0x7b] 3598 1 T47 1 T160 21 T62 2
valid_sources[0x7c] 3310 1 T10 2 T54 9 T11 1
valid_sources[0x7d] 2675 1 T30 1 T31 11 T136 1
valid_sources[0x7e] 3337 1 T24 5 T161 15 T137 1
valid_sources[0x7f] 3268 1 T11 1 T15 2 T62 15
valid_sources[0x80] 4095 1 T24 1 T15 1 T62 10



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 306482 1 T6 80 T2 1 T27 6
values[0x0] all_enables biggest_size 147368 1 T2 1 T3 3 T4 1
values[0x1] all_enables biggest_size 146362 1 T1 2 T2 3 T3 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5339 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 15063 1 T32 5 T33 1 T43 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 9150 1 T62 38 T63 12 T64 32
values[0x0] 5550 1 T32 8 T33 7 T43 11
values[0x1] 5702 1 T32 4 T33 4 T43 9



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4090 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 16312 1 T32 5 T33 3 T43 7



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 66 1 T62 1 T69 1 T87 1
valid_sources[0x01] 87 1 T69 1 T85 1 T87 1
valid_sources[0x02] 44 1 T162 1 T62 2 T69 2
valid_sources[0x03] 81 1 T33 11 T163 1 T69 2
valid_sources[0x04] 50 1 T32 1 T164 1 T165 1
valid_sources[0x05] 54 1 T63 3 T69 2 T91 1
valid_sources[0x06] 107 1 T166 1 T167 2 T69 4
valid_sources[0x07] 46 1 T62 1 T85 1 T78 2
valid_sources[0x08] 93 1 T168 1 T169 6 T167 1
valid_sources[0x09] 76 1 T62 1 T69 4 T85 3
valid_sources[0x0a] 94 1 T32 1 T69 3 T83 6
valid_sources[0x0b] 69 1 T170 3 T85 1 T76 3
valid_sources[0x0c] 45 1 T171 1 T69 1 T85 2
valid_sources[0x0d] 61 1 T68 1 T62 1 T69 3
valid_sources[0x0e] 91 1 T62 1 T85 1 T80 1
valid_sources[0x0f] 71 1 T43 20 T44 1 T69 5
valid_sources[0x10] 86 1 T116 2 T172 1 T165 2
valid_sources[0x11] 68 1 T62 1 T69 2 T85 2
valid_sources[0x12] 74 1 T37 7 T69 7 T125 3
valid_sources[0x13] 49 1 T72 3 T62 1 T69 4
valid_sources[0x14] 122 1 T173 3 T63 5 T69 2
valid_sources[0x15] 68 1 T174 9 T62 2 T69 2
valid_sources[0x16] 94 1 T69 2 T70 1 T78 2
valid_sources[0x17] 76 1 T62 1 T69 2 T82 2
valid_sources[0x18] 91 1 T166 1 T62 1 T69 1
valid_sources[0x19] 80 1 T175 3 T69 1 T70 2
valid_sources[0x1a] 101 1 T167 1 T62 1 T70 1
valid_sources[0x1b] 92 1 T62 1 T64 3 T69 2
valid_sources[0x1c] 59 1 T69 2 T85 2 T91 1
valid_sources[0x1d] 62 1 T62 1 T69 2 T95 1
valid_sources[0x1e] 60 1 T176 6 T170 1 T104 1
valid_sources[0x1f] 101 1 T62 1 T69 2 T74 4
valid_sources[0x20] 79 1 T171 1 T69 4 T78 3
valid_sources[0x21] 890 1 T62 1 T69 4 T86 768
valid_sources[0x22] 95 1 T177 1 T62 1 T69 2
valid_sources[0x23] 95 1 T69 2 T70 2 T85 2
valid_sources[0x24] 55 1 T69 2 T70 2 T125 2
valid_sources[0x25] 61 1 T119 1 T96 1 T78 2
valid_sources[0x26] 99 1 T37 8 T69 5 T82 4
valid_sources[0x27] 57 1 T167 1 T74 1 T95 1
valid_sources[0x28] 321 1 T69 1 T85 1 T76 1
valid_sources[0x29] 65 1 T178 1 T179 1 T69 2
valid_sources[0x2a] 78 1 T180 1 T69 3 T80 3
valid_sources[0x2b] 87 1 T62 1 T69 4 T70 3
valid_sources[0x2c] 48 1 T69 1 T120 1 T128 1
valid_sources[0x2d] 63 1 T118 1 T69 1 T87 1
valid_sources[0x2e] 63 1 T69 1 T85 1 T78 3
valid_sources[0x2f] 62 1 T171 1 T69 2 T91 1
valid_sources[0x30] 64 1 T69 5 T78 2 T80 1
valid_sources[0x31] 71 1 T176 1 T69 1 T70 1
valid_sources[0x32] 76 1 T69 1 T85 1 T74 1
valid_sources[0x33] 52 1 T62 1 T91 1 T78 4
valid_sources[0x34] 54 1 T171 1 T69 2 T78 2
valid_sources[0x35] 48 1 T170 1 T181 3 T74 3
valid_sources[0x36] 43 1 T168 1 T182 3 T62 2
valid_sources[0x37] 36 1 T62 1 T69 1 T87 1
valid_sources[0x38] 61 1 T167 1 T62 1 T69 3
valid_sources[0x39] 72 1 T62 1 T69 1 T85 2
valid_sources[0x3a] 83 1 T69 3 T85 5 T78 2
valid_sources[0x3b] 56 1 T167 1 T62 1 T69 1
valid_sources[0x3c] 64 1 T166 1 T167 2 T63 15
valid_sources[0x3d] 72 1 T166 1 T69 2 T85 1
valid_sources[0x3e] 55 1 T116 2 T69 5 T70 1
valid_sources[0x3f] 37 1 T119 1 T87 1 T74 1
valid_sources[0x40] 51 1 T119 1 T69 5 T74 1
valid_sources[0x41] 113 1 T183 9 T62 1 T69 4
valid_sources[0x42] 87 1 T44 2 T184 14 T69 2
valid_sources[0x43] 81 1 T69 2 T70 1 T96 7
valid_sources[0x44] 63 1 T171 1 T69 2 T85 1
valid_sources[0x45] 132 1 T170 1 T69 3 T107 3
valid_sources[0x46] 38 1 T178 1 T69 1 T78 1
valid_sources[0x47] 56 1 T119 1 T70 1 T87 1
valid_sources[0x48] 51 1 T116 1 T63 1 T69 2
valid_sources[0x49] 63 1 T119 1 T185 1 T62 1
valid_sources[0x4a] 64 1 T168 1 T186 2 T62 1
valid_sources[0x4b] 42 1 T78 1 T80 2 T126 1
valid_sources[0x4c] 51 1 T166 2 T62 1 T69 2
valid_sources[0x4d] 110 1 T167 1 T62 1 T69 1
valid_sources[0x4e] 46 1 T69 2 T91 2 T78 1
valid_sources[0x4f] 43 1 T69 3 T78 5 T80 1
valid_sources[0x50] 46 1 T187 1 T69 2 T74 2
valid_sources[0x51] 92 1 T188 1 T189 3 T64 11
valid_sources[0x52] 49 1 T116 1 T69 1 T85 3
valid_sources[0x53] 76 1 T62 1 T69 1 T85 3
valid_sources[0x54] 70 1 T190 22 T171 1 T69 2
valid_sources[0x55] 63 1 T62 1 T69 2 T74 1
valid_sources[0x56] 64 1 T85 2 T77 11 T80 2
valid_sources[0x57] 88 1 T167 1 T180 1 T191 14
valid_sources[0x58] 67 1 T176 5 T62 1 T69 2
valid_sources[0x59] 72 1 T192 1 T62 1 T69 2
valid_sources[0x5a] 58 1 T69 1 T85 1 T90 4
valid_sources[0x5b] 161 1 T193 6 T181 1 T62 1
valid_sources[0x5c] 133 1 T62 2 T69 1 T85 1
valid_sources[0x5d] 79 1 T62 1 T69 1 T82 9
valid_sources[0x5e] 102 1 T194 12 T62 2 T69 2
valid_sources[0x5f] 38 1 T62 1 T69 1 T85 1
valid_sources[0x60] 83 1 T62 1 T69 1 T85 4
valid_sources[0x61] 831 1 T69 2 T85 2 T87 1
valid_sources[0x62] 45 1 T69 2 T82 4 T70 2
valid_sources[0x63] 65 1 T72 2 T69 3 T85 1
valid_sources[0x64] 54 1 T69 3 T85 1 T74 1
valid_sources[0x65] 89 1 T72 7 T69 3 T78 1
valid_sources[0x66] 64 1 T64 9 T69 1 T89 2
valid_sources[0x67] 72 1 T69 5 T85 2 T91 2
valid_sources[0x68] 49 1 T69 1 T85 1 T78 2
valid_sources[0x69] 48 1 T119 1 T192 1 T69 2
valid_sources[0x6a] 65 1 T167 1 T62 1 T70 1
valid_sources[0x6b] 79 1 T64 15 T85 6 T76 1
valid_sources[0x6c] 71 1 T170 1 T69 3 T70 1
valid_sources[0x6d] 58 1 T32 1 T69 1 T70 1
valid_sources[0x6e] 95 1 T69 1 T85 1 T90 6
valid_sources[0x6f] 63 1 T185 1 T192 1 T69 1
valid_sources[0x70] 63 1 T164 1 T69 5 T85 1
valid_sources[0x71] 63 1 T170 1 T69 1 T74 5
valid_sources[0x72] 58 1 T119 1 T62 1 T85 2
valid_sources[0x73] 63 1 T62 1 T69 2 T70 1
valid_sources[0x74] 127 1 T62 1 T69 2 T70 1
valid_sources[0x75] 145 1 T44 2 T62 1 T69 1
valid_sources[0x76] 41 1 T69 2 T70 1 T85 2
valid_sources[0x77] 43 1 T36 5 T186 1 T69 4
valid_sources[0x78] 111 1 T117 1 T182 2 T69 3
valid_sources[0x79] 71 1 T69 1 T83 9 T78 3
valid_sources[0x7a] 64 1 T68 2 T185 1 T62 1
valid_sources[0x7b] 100 1 T64 3 T69 1 T78 2
valid_sources[0x7c] 51 1 T178 2 T70 1 T85 2
valid_sources[0x7d] 79 1 T64 7 T69 2 T85 3
valid_sources[0x7e] 106 1 T164 6 T171 1 T62 4
valid_sources[0x7f] 56 1 T62 1 T69 4 T195 1
valid_sources[0x80] 69 1 T187 1 T69 2 T85 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 5901 1 T62 29 T63 9 T64 13
values[0x0] all_enables biggest_size 4707 1 T32 4 T33 1 T43 2
values[0x1] all_enables biggest_size 4455 1 T32 1 T43 1 T44 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%