Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	262931	1		T1	6		T2	7		T3	13
full_word	601331	1		T1	2		T6	80		T2	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	863922	1		T1	8		T6	80		T2	12
auto[TlIntgErrCmd]	118	1		T64	4		T70	3		T79	9
auto[TlIntgErrData]	105	1		T64	1		T70	5		T79	5
auto[TlIntgErrBoth]	117	1		T64	5		T70	2		T79	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	523739	1		T6	80		T2	2		T27	18
auto[1]	340523	1		T1	8		T2	10		T3	17

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	216979	1		T2	1		T27	12		T5	2
auto[TlIntgErrNone]	partial	auto[1]	45640	1		T1	6		T2	6		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	306608	1		T6	80		T2	1		T27	6
auto[TlIntgErrNone]	full_word	auto[1]	294695	1		T1	2		T2	4		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	48	1		T70	2		T79	3		T125	4
auto[TlIntgErrCmd]	partial	auto[1]	61	1		T64	4		T70	1		T79	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T79	1		T125	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T126	2		T128	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T70	3		T79	2		T125	2
auto[TlIntgErrData]	partial	auto[1]	52	1		T64	1		T70	2		T79	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T126	1		T131	1		T129	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T126	1		T129	2		T132	2
auto[TlIntgErrBoth]	partial	auto[0]	49	1		T64	2		T79	4		T125	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T64	2		T70	2		T79	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T128	1		T133	1		T134	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T64	1		T125	1		T128	1