Unified Coverage Report :: Module :: prim_fifo_async_simple

Module : prim_fifo_async_simple

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	87.50			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.dap.i_dmi_cdc.i_cdc_req	95.83	100.00	87.50			100.00
tb.dut.dap.i_dmi_cdc.i_cdc_resp	97.78	100.00	93.33			100.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	87.50			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.95	100.00	81.82			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		i_dmi_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	79.17	100.00	66.67			100.00	50.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.78	100.00	93.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.04	100.00	85.71			96.43	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		i_dmi_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	77.98	100.00	66.67			95.24	50.00

Line Coverage for Module : prim_fifo_async_simple

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	51	5	5	100.00
ALWAYS	85	2	2	100.00
CONT_ASSIGN	89	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1
43	1	1
47	1	1
48	1	1
51	1	1
52	1	1
53	1	1
55	1	1
56	1	1
85	1	1
86	1	1
			MISSING_ELSE
89	1	1

---

Cond Coverage for Module : prim_fifo_async_simple

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!pending_q)) && not_in_reset_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       40
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Not Covered
1	1	Covered	T1,T6,T2

 LINE       41
 EXPRESSION (pending_q || wvalid_i)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2

 LINE       43
 EXPRESSION (src_ack ? 1'b0 : (wr_en ? 1'b1 : pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T6,T2

 LINE       43
 SUB-EXPRESSION (wr_en ? 1'b1 : pending_q)
                 --1--

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T6,T2

 LINE       48
 EXPRESSION (dst_req && rready_i)
             ---1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Not Covered
1	1	Covered	T1,T6,T2

---

Branch Coverage for Module : prim_fifo_async_simple

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	43	3	3	100.00
IF	51	2	2	100.00
IF	85	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	43	(src_ack) ? 
-2-:	43	(wr_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T6,T2
0	1	Covered	T1,T6,T2
0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	51	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T2
0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	85	if (wr_en)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T2
0	Covered	T1,T6,T2

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	51	5	5	100.00
ALWAYS	85	2	2	100.00
CONT_ASSIGN	89	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1
43	1	1
47	1	1
48	1	1
51	1	1
52	1	1
53	1	1
55	1	1
56	1	1
85	1	1
86	1	1
			MISSING_ELSE
89	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!pending_q)) && not_in_reset_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       40
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Not Covered
1	1	Covered	T1,T6,T2

 LINE       41
 EXPRESSION (pending_q || wvalid_i)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2

 LINE       43
 EXPRESSION (src_ack ? 1'b0 : (wr_en ? 1'b1 : pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T6,T2

 LINE       43
 SUB-EXPRESSION (wr_en ? 1'b1 : pending_q)
                 --1--

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T6,T2

 LINE       48
 EXPRESSION (dst_req && rready_i)
             ---1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Not Covered
1	1	Covered	T1,T6,T2

---

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	43	3	3	100.00
IF	51	2	2	100.00
IF	85	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	43	(src_ack) ? 
-2-:	43	(wr_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T6,T2
0	1	Covered	T1,T6,T2
0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	51	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T2
0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	85	if (wr_en)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T2
0	Covered	T1,T6,T2

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	51	5	5	100.00
ALWAYS	85	2	2	100.00
CONT_ASSIGN	89	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1
43	1	1
47	1	1
48	1	1
51	1	1
52	1	1
53	1	1
55	1	1
56	1	1
85	1	1
86	1	1
			MISSING_ELSE
89	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!pending_q)) && not_in_reset_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       40
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Not Covered
1	1	Covered	T1,T6,T2

 LINE       41
 EXPRESSION (pending_q || wvalid_i)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T2
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2

 LINE       43
 EXPRESSION (src_ack ? 1'b0 : (wr_en ? 1'b1 : pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T6,T2

 LINE       43
 SUB-EXPRESSION (wr_en ? 1'b1 : pending_q)
                 --1--

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T6,T2

 LINE       48
 EXPRESSION (dst_req && rready_i)
             ---1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Unreachable
1	1	Covered	T1,T6,T2

---

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	43	3	3	100.00
IF	51	2	2	100.00
IF	85	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	43	(src_ack) ? 
-2-:	43	(wr_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T6,T2
0	1	Covered	T1,T6,T2
0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	51	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T2
0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	85	if (wr_en)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T2
0	Covered	T1,T6,T2