Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dm_top.i_dm_csrs.i_fifo	90.62	100.00	62.50			100.00	100.00

---

Module Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.06	100.00	77.78			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
68.23	85.56	62.67			56.47		i_dm_csrs

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Not Covered
1	1	Covered	T1,T6,T2

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T2
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T2

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T2
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T2

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (34'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T1,T6,T2

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T2
0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T6,T2
0	1	Covered	T1,T6,T2
0	0	Covered	T1,T6,T2

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T2
0	Covered	T1,T6,T2

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	49647471	22115	0	0
DepthKnown_A	49647471	48366850	0	0
RvalidKnown_A	49647471	48366850	0	0
WreadyKnown_A	49647471	48366850	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	49647471	22115	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49647471	22115	0	0
T1	49234	25	0	0
T2	90244	184	0	0
T3	495591	160	0	0
T4	9278	11	0	0
T6	1792	1	0	0
T12	121624	83	0	0
T13	160291	74	0	0
T18	25863	31	0	0
T32	3255	1	0	0
T33	2524	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49647471	48366850	0	0
T1	49234	49107	0	0
T2	90244	89852	0	0
T3	495591	492870	0	0
T4	9278	9217	0	0
T6	1792	1711	0	0
T12	121624	121215	0	0
T13	160291	159937	0	0
T18	25863	25763	0	0
T32	3255	2939	0	0
T33	2524	2431	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49647471	48366850	0	0
T1	49234	49107	0	0
T2	90244	89852	0	0
T3	495591	492870	0	0
T4	9278	9217	0	0
T6	1792	1711	0	0
T12	121624	121215	0	0
T13	160291	159937	0	0
T18	25863	25763	0	0
T32	3255	2939	0	0
T33	2524	2431	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49647471	48366850	0	0
T1	49234	49107	0	0
T2	90244	89852	0	0
T3	495591	492870	0	0
T4	9278	9217	0	0
T6	1792	1711	0	0
T12	121624	121215	0	0
T13	160291	159937	0	0
T18	25863	25763	0	0
T32	3255	2939	0	0
T33	2524	2431	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	49647471	22115	0	0
T1	49234	25	0	0
T2	90244	184	0	0
T3	495591	160	0	0
T4	9278	11	0	0
T6	1792	1	0	0
T12	121624	83	0	0
T13	160291	74	0	0
T18	25863	31	0	0
T32	3255	1	0	0
T33	2524	1	0	0