Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T6,T2 |
0 | 1 | Covered | T1,T6,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T6,T2 |
1 | 1 | Covered | T1,T6,T2 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
8905673 |
8904362 |
0 |
0 |
selKnown1 |
55867332 |
55866015 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8905673 |
8904362 |
0 |
0 |
T1 |
6225 |
6223 |
0 |
0 |
T2 |
59151 |
59147 |
0 |
0 |
T3 |
42632 |
42628 |
0 |
0 |
T4 |
3139 |
3135 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
926 |
924 |
0 |
0 |
T12 |
19622 |
19618 |
0 |
0 |
T13 |
17223 |
17219 |
0 |
0 |
T14 |
2 |
0 |
0 |
0 |
T18 |
9853 |
9849 |
0 |
0 |
T19 |
2 |
0 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T27 |
0 |
12 |
0 |
0 |
T30 |
0 |
10 |
0 |
0 |
T31 |
0 |
10 |
0 |
0 |
T32 |
396 |
392 |
0 |
0 |
T33 |
454 |
450 |
0 |
0 |
T56 |
0 |
20 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55867332 |
55866015 |
0 |
0 |
T1 |
52346 |
52344 |
0 |
0 |
T2 |
119821 |
119817 |
0 |
0 |
T3 |
516913 |
516909 |
0 |
0 |
T4 |
10848 |
10844 |
0 |
0 |
T5 |
0 |
2 |
0 |
0 |
T6 |
2255 |
2253 |
0 |
0 |
T12 |
131438 |
131434 |
0 |
0 |
T13 |
168903 |
168899 |
0 |
0 |
T14 |
2 |
0 |
0 |
0 |
T18 |
30790 |
30786 |
0 |
0 |
T19 |
2 |
0 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
0 |
8 |
0 |
0 |
T27 |
0 |
6 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T31 |
0 |
10 |
0 |
0 |
T32 |
3454 |
3450 |
0 |
0 |
T33 |
2752 |
2748 |
0 |
0 |
T56 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T6,T2 |
0 | 1 | Covered | T1,T6,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T6,T2 |
1 | 1 | Covered | T1,T6,T2 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2685222 |
2685000 |
0 |
0 |
selKnown1 |
49647471 |
49647246 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2685222 |
2685000 |
0 |
0 |
T1 |
3112 |
3111 |
0 |
0 |
T2 |
29567 |
29566 |
0 |
0 |
T3 |
21308 |
21307 |
0 |
0 |
T4 |
1568 |
1567 |
0 |
0 |
T6 |
463 |
462 |
0 |
0 |
T12 |
9808 |
9807 |
0 |
0 |
T13 |
8610 |
8609 |
0 |
0 |
T18 |
4925 |
4924 |
0 |
0 |
T32 |
197 |
196 |
0 |
0 |
T33 |
226 |
225 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
49647471 |
49647246 |
0 |
0 |
T1 |
49234 |
49233 |
0 |
0 |
T2 |
90244 |
90243 |
0 |
0 |
T3 |
495591 |
495590 |
0 |
0 |
T4 |
9278 |
9277 |
0 |
0 |
T6 |
1792 |
1791 |
0 |
0 |
T12 |
121624 |
121623 |
0 |
0 |
T13 |
160291 |
160290 |
0 |
0 |
T18 |
25863 |
25862 |
0 |
0 |
T32 |
3255 |
3254 |
0 |
0 |
T33 |
2524 |
2523 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T6,T2 |
0 | 1 | Covered | T1,T6,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T6,T2 |
1 | 1 | Covered | T1,T6,T2 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
700 |
478 |
0 |
0 |
T2 |
5 |
4 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
1 |
0 |
0 |
T12 |
3 |
2 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T27 |
0 |
6 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T31 |
0 |
5 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T56 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
593 |
368 |
0 |
0 |
T2 |
5 |
4 |
0 |
0 |
T3 |
7 |
6 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
1 |
0 |
0 |
T12 |
3 |
2 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T27 |
0 |
3 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T31 |
0 |
5 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T56 |
0 |
10 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T6,T2 |
0 | 1 | Covered | T1,T6,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T6,T2 |
1 | 1 | Covered | T1,T6,T2 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6217932 |
6217497 |
0 |
0 |
selKnown1 |
6217730 |
6217298 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6217932 |
6217497 |
0 |
0 |
T1 |
3113 |
3112 |
0 |
0 |
T2 |
29567 |
29566 |
0 |
0 |
T3 |
21309 |
21308 |
0 |
0 |
T4 |
1569 |
1568 |
0 |
0 |
T6 |
463 |
462 |
0 |
0 |
T12 |
9808 |
9807 |
0 |
0 |
T13 |
8611 |
8610 |
0 |
0 |
T18 |
4926 |
4925 |
0 |
0 |
T32 |
197 |
196 |
0 |
0 |
T33 |
226 |
225 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6217730 |
6217298 |
0 |
0 |
T1 |
3112 |
3111 |
0 |
0 |
T2 |
29567 |
29566 |
0 |
0 |
T3 |
21308 |
21307 |
0 |
0 |
T4 |
1568 |
1567 |
0 |
0 |
T6 |
463 |
462 |
0 |
0 |
T12 |
9808 |
9807 |
0 |
0 |
T13 |
8610 |
8609 |
0 |
0 |
T18 |
4925 |
4924 |
0 |
0 |
T32 |
197 |
196 |
0 |
0 |
T33 |
226 |
225 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T6,T2 |
0 | 1 | Covered | T1,T6,T2 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T2 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T6,T2 |
1 | 1 | Covered | T1,T6,T2 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1819 |
1387 |
0 |
0 |
selKnown1 |
1538 |
1103 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1819 |
1387 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
1 |
0 |
0 |
T12 |
3 |
2 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T27 |
0 |
6 |
0 |
0 |
T30 |
0 |
9 |
0 |
0 |
T31 |
0 |
5 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T56 |
0 |
10 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1538 |
1103 |
0 |
0 |
T2 |
5 |
4 |
0 |
0 |
T3 |
7 |
6 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
0 |
1 |
0 |
0 |
T12 |
3 |
2 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
0 |
4 |
0 |
0 |
T27 |
0 |
3 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T31 |
0 |
5 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T56 |
0 |
10 |
0 |
0 |