Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
81.22 95.27 79.17 88.93 66.67 85.17 98.32 55.01


Total test records in report: 432
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T96 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2345874088 Jun 26 06:26:17 PM PDT 24 Jun 26 06:27:16 PM PDT 24 7395921743 ps
T97 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3085919308 Jun 26 06:26:38 PM PDT 24 Jun 26 06:26:46 PM PDT 24 1687320810 ps
T82 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1689078464 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:54 PM PDT 24 3194822329 ps
T98 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.473722225 Jun 26 06:26:22 PM PDT 24 Jun 26 06:26:26 PM PDT 24 508638687 ps
T298 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1716186096 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:34 PM PDT 24 324581393 ps
T299 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.489136074 Jun 26 06:26:39 PM PDT 24 Jun 26 06:26:43 PM PDT 24 3365417939 ps
T300 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1662595050 Jun 26 06:26:46 PM PDT 24 Jun 26 06:26:48 PM PDT 24 100128758 ps
T301 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2219361107 Jun 26 06:26:29 PM PDT 24 Jun 26 06:27:38 PM PDT 24 25456981816 ps
T302 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3594001979 Jun 26 06:26:17 PM PDT 24 Jun 26 06:26:21 PM PDT 24 2458132890 ps
T83 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3442083234 Jun 26 06:26:39 PM PDT 24 Jun 26 06:26:47 PM PDT 24 3184483811 ps
T122 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3782417816 Jun 26 06:26:40 PM PDT 24 Jun 26 06:26:44 PM PDT 24 381198154 ps
T303 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1081534486 Jun 26 06:26:46 PM PDT 24 Jun 26 06:27:06 PM PDT 24 22333575752 ps
T103 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3481023434 Jun 26 06:26:19 PM PDT 24 Jun 26 06:27:18 PM PDT 24 5723690815 ps
T84 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2627531898 Jun 26 06:26:48 PM PDT 24 Jun 26 06:26:59 PM PDT 24 1506921581 ps
T85 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.809407905 Jun 26 06:26:38 PM PDT 24 Jun 26 06:26:42 PM PDT 24 80087587 ps
T304 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.923592217 Jun 26 06:26:29 PM PDT 24 Jun 26 06:26:30 PM PDT 24 104182259 ps
T305 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1100493217 Jun 26 06:26:22 PM PDT 24 Jun 26 06:26:27 PM PDT 24 2669536639 ps
T306 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2398963370 Jun 26 06:26:48 PM PDT 24 Jun 26 06:27:01 PM PDT 24 9558195228 ps
T307 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2367699497 Jun 26 06:26:37 PM PDT 24 Jun 26 06:26:39 PM PDT 24 199347664 ps
T86 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3292696461 Jun 26 06:26:34 PM PDT 24 Jun 26 06:26:37 PM PDT 24 346434339 ps
T99 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1086887297 Jun 26 06:26:16 PM PDT 24 Jun 26 06:26:23 PM PDT 24 2385659226 ps
T133 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3690800180 Jun 26 06:26:16 PM PDT 24 Jun 26 06:26:22 PM PDT 24 1465360631 ps
T104 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2875811004 Jun 26 06:26:24 PM PDT 24 Jun 26 06:26:33 PM PDT 24 374667044 ps
T125 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2820659203 Jun 26 06:26:29 PM PDT 24 Jun 26 06:26:34 PM PDT 24 207203609 ps
T308 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.746130782 Jun 26 06:26:11 PM PDT 24 Jun 26 06:26:13 PM PDT 24 312734250 ps
T309 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2021164888 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:39 PM PDT 24 976371765 ps
T123 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3760466058 Jun 26 06:26:30 PM PDT 24 Jun 26 06:26:33 PM PDT 24 45621407 ps
T134 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2627142742 Jun 26 06:26:40 PM PDT 24 Jun 26 06:26:48 PM PDT 24 4463338475 ps
T113 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.657455171 Jun 26 06:26:45 PM PDT 24 Jun 26 06:26:48 PM PDT 24 221943169 ps
T310 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.856525751 Jun 26 06:26:08 PM PDT 24 Jun 26 06:27:28 PM PDT 24 57488575151 ps
T114 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1723521098 Jun 26 06:26:45 PM PDT 24 Jun 26 06:26:50 PM PDT 24 503865620 ps
T126 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.4212614597 Jun 26 06:26:09 PM PDT 24 Jun 26 06:26:13 PM PDT 24 185834495 ps
T311 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3601640504 Jun 26 06:26:28 PM PDT 24 Jun 26 06:26:33 PM PDT 24 894832795 ps
T312 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1244158910 Jun 26 06:26:06 PM PDT 24 Jun 26 06:26:12 PM PDT 24 4780255486 ps
T141 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3911837944 Jun 26 06:26:24 PM PDT 24 Jun 26 06:26:46 PM PDT 24 1395657934 ps
T313 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2823159462 Jun 26 06:26:23 PM PDT 24 Jun 26 06:26:30 PM PDT 24 1937650084 ps
T115 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.807726249 Jun 26 06:26:07 PM PDT 24 Jun 26 06:27:24 PM PDT 24 9123866375 ps
T314 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3906811926 Jun 26 06:26:09 PM PDT 24 Jun 26 06:26:11 PM PDT 24 74952195 ps
T315 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3307119820 Jun 26 06:26:32 PM PDT 24 Jun 26 06:26:35 PM PDT 24 1553979810 ps
T316 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.824766301 Jun 26 06:26:10 PM PDT 24 Jun 26 06:26:17 PM PDT 24 6063981919 ps
T317 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2145615628 Jun 26 06:26:48 PM PDT 24 Jun 26 06:26:50 PM PDT 24 250597338 ps
T116 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.361801859 Jun 26 06:26:23 PM PDT 24 Jun 26 06:26:29 PM PDT 24 116995444 ps
T117 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3406793962 Jun 26 06:26:16 PM PDT 24 Jun 26 06:26:20 PM PDT 24 101622513 ps
T318 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2147438158 Jun 26 06:26:44 PM PDT 24 Jun 26 06:26:58 PM PDT 24 4750130965 ps
T105 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3691889058 Jun 26 06:26:23 PM PDT 24 Jun 26 06:26:27 PM PDT 24 94115402 ps
T100 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1822350044 Jun 26 06:26:18 PM PDT 24 Jun 26 06:26:24 PM PDT 24 8788126924 ps
T106 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3661258981 Jun 26 06:26:09 PM PDT 24 Jun 26 06:26:14 PM PDT 24 306756729 ps
T319 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1689234704 Jun 26 06:26:09 PM PDT 24 Jun 26 06:28:11 PM PDT 24 50895010899 ps
T320 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2650236426 Jun 26 06:26:23 PM PDT 24 Jun 26 06:26:32 PM PDT 24 1920597532 ps
T127 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.648783527 Jun 26 06:26:48 PM PDT 24 Jun 26 06:26:53 PM PDT 24 442738185 ps
T107 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3835762694 Jun 26 06:26:22 PM PDT 24 Jun 26 06:26:31 PM PDT 24 440838763 ps
T321 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3898473443 Jun 26 06:26:50 PM PDT 24 Jun 26 06:26:59 PM PDT 24 2808895688 ps
T108 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2141006917 Jun 26 06:26:19 PM PDT 24 Jun 26 06:27:28 PM PDT 24 6361819743 ps
T322 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2182059743 Jun 26 06:26:39 PM PDT 24 Jun 26 06:26:44 PM PDT 24 1883246923 ps
T119 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.888926103 Jun 26 06:26:21 PM PDT 24 Jun 26 06:26:26 PM PDT 24 491861299 ps
T323 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2890976637 Jun 26 06:26:38 PM PDT 24 Jun 26 06:27:03 PM PDT 24 32993067123 ps
T324 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3205128593 Jun 26 06:26:07 PM PDT 24 Jun 26 06:26:10 PM PDT 24 261804469 ps
T325 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2144132105 Jun 26 06:26:36 PM PDT 24 Jun 26 06:26:39 PM PDT 24 76616390 ps
T109 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.416709856 Jun 26 06:26:20 PM PDT 24 Jun 26 06:26:28 PM PDT 24 863331127 ps
T326 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2349034515 Jun 26 06:26:46 PM PDT 24 Jun 26 06:26:52 PM PDT 24 213094512 ps
T327 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4184364118 Jun 26 06:26:44 PM PDT 24 Jun 26 06:26:48 PM PDT 24 146899942 ps
T135 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.519116702 Jun 26 06:26:44 PM PDT 24 Jun 26 06:26:58 PM PDT 24 2329851630 ps
T328 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4161116305 Jun 26 06:26:24 PM PDT 24 Jun 26 06:26:28 PM PDT 24 853084086 ps
T128 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1599428015 Jun 26 06:26:10 PM PDT 24 Jun 26 06:26:16 PM PDT 24 1984149294 ps
T329 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.64420457 Jun 26 06:26:20 PM PDT 24 Jun 26 06:28:26 PM PDT 24 49324688717 ps
T330 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1704172762 Jun 26 06:26:32 PM PDT 24 Jun 26 06:26:35 PM PDT 24 193542226 ps
T110 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.140325116 Jun 26 06:26:23 PM PDT 24 Jun 26 06:26:30 PM PDT 24 345062771 ps
T140 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2394785814 Jun 26 06:26:30 PM PDT 24 Jun 26 06:26:51 PM PDT 24 2905674019 ps
T129 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3199828503 Jun 26 06:26:29 PM PDT 24 Jun 26 06:26:38 PM PDT 24 2329120345 ps
T111 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1477614988 Jun 26 06:26:22 PM PDT 24 Jun 26 06:26:26 PM PDT 24 202812202 ps
T331 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4115604182 Jun 26 06:26:47 PM PDT 24 Jun 26 06:26:53 PM PDT 24 1503050683 ps
T332 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3509158949 Jun 26 06:26:29 PM PDT 24 Jun 26 06:26:31 PM PDT 24 480207580 ps
T333 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.248559630 Jun 26 06:26:15 PM PDT 24 Jun 26 06:26:20 PM PDT 24 171388268 ps
T334 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1477369328 Jun 26 06:26:08 PM PDT 24 Jun 26 06:26:15 PM PDT 24 189665384 ps
T138 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2479134944 Jun 26 06:26:39 PM PDT 24 Jun 26 06:27:00 PM PDT 24 2243380014 ps
T335 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.720198962 Jun 26 06:26:27 PM PDT 24 Jun 26 06:26:30 PM PDT 24 754694877 ps
T101 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.278779991 Jun 26 06:26:06 PM PDT 24 Jun 26 06:26:25 PM PDT 24 6889654335 ps
T336 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3236433007 Jun 26 06:26:32 PM PDT 24 Jun 26 06:27:42 PM PDT 24 47826911561 ps
T337 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3755288178 Jun 26 06:26:30 PM PDT 24 Jun 26 06:26:34 PM PDT 24 370227756 ps
T338 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.559321065 Jun 26 06:26:24 PM PDT 24 Jun 26 06:26:29 PM PDT 24 878715891 ps
T339 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.971941881 Jun 26 06:26:21 PM PDT 24 Jun 26 06:26:24 PM PDT 24 127616350 ps
T120 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.57051538 Jun 26 06:26:32 PM PDT 24 Jun 26 06:26:42 PM PDT 24 2200175195 ps
T340 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2600857084 Jun 26 06:26:16 PM PDT 24 Jun 26 06:26:22 PM PDT 24 1860838004 ps
T121 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3506735842 Jun 26 06:26:48 PM PDT 24 Jun 26 06:26:54 PM PDT 24 202239669 ps
T341 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.769313414 Jun 26 06:26:47 PM PDT 24 Jun 26 06:27:08 PM PDT 24 24180005616 ps
T342 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.576457638 Jun 26 06:26:32 PM PDT 24 Jun 26 06:26:36 PM PDT 24 154947172 ps
T343 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3030726017 Jun 26 06:26:07 PM PDT 24 Jun 26 06:26:10 PM PDT 24 400745306 ps
T344 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2970193784 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:45 PM PDT 24 4508956010 ps
T345 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2859954241 Jun 26 06:26:37 PM PDT 24 Jun 26 06:26:39 PM PDT 24 36711752 ps
T346 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3287280620 Jun 26 06:26:48 PM PDT 24 Jun 26 06:26:54 PM PDT 24 236556391 ps
T347 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4062141977 Jun 26 06:26:22 PM PDT 24 Jun 26 06:26:25 PM PDT 24 45860869 ps
T348 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2787876057 Jun 26 06:26:48 PM PDT 24 Jun 26 06:26:56 PM PDT 24 600109323 ps
T349 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3389721604 Jun 26 06:26:45 PM PDT 24 Jun 26 06:26:50 PM PDT 24 102869194 ps
T350 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3625670065 Jun 26 06:26:18 PM PDT 24 Jun 26 06:26:38 PM PDT 24 6819968987 ps
T136 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4094818180 Jun 26 06:26:44 PM PDT 24 Jun 26 06:26:58 PM PDT 24 4177164474 ps
T351 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1406196057 Jun 26 06:26:24 PM PDT 24 Jun 26 06:26:29 PM PDT 24 208176326 ps
T352 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3077844111 Jun 26 06:26:39 PM PDT 24 Jun 26 06:26:42 PM PDT 24 1910283057 ps
T353 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1604053636 Jun 26 06:26:10 PM PDT 24 Jun 26 06:28:31 PM PDT 24 100117999914 ps
T354 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3353223685 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:45 PM PDT 24 25817111723 ps
T355 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4206265883 Jun 26 06:26:09 PM PDT 24 Jun 26 06:27:51 PM PDT 24 34038988022 ps
T356 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2929978534 Jun 26 06:26:29 PM PDT 24 Jun 26 06:26:38 PM PDT 24 4781692305 ps
T357 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3855060822 Jun 26 06:26:58 PM PDT 24 Jun 26 06:27:09 PM PDT 24 7430054587 ps
T358 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.85240084 Jun 26 06:26:46 PM PDT 24 Jun 26 06:26:49 PM PDT 24 394230052 ps
T359 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2794323086 Jun 26 06:26:22 PM PDT 24 Jun 26 06:26:28 PM PDT 24 436083987 ps
T360 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3597592302 Jun 26 06:26:44 PM PDT 24 Jun 26 06:26:49 PM PDT 24 297750578 ps
T361 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3629763708 Jun 26 06:26:23 PM PDT 24 Jun 26 06:26:27 PM PDT 24 1222261197 ps
T362 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3255866724 Jun 26 06:26:39 PM PDT 24 Jun 26 06:26:48 PM PDT 24 5154656636 ps
T363 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3552994753 Jun 26 06:26:10 PM PDT 24 Jun 26 06:26:27 PM PDT 24 34965251462 ps
T112 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2253863302 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:41 PM PDT 24 6405527976 ps
T364 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2494501795 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:37 PM PDT 24 162486095 ps
T137 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1988698992 Jun 26 06:26:07 PM PDT 24 Jun 26 06:26:40 PM PDT 24 5456473028 ps
T365 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1421590911 Jun 26 06:26:37 PM PDT 24 Jun 26 06:26:40 PM PDT 24 158867967 ps
T366 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2229718599 Jun 26 06:26:57 PM PDT 24 Jun 26 06:27:02 PM PDT 24 921257336 ps
T139 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1272848184 Jun 26 06:26:08 PM PDT 24 Jun 26 06:26:30 PM PDT 24 2070072373 ps
T367 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1534511804 Jun 26 06:26:26 PM PDT 24 Jun 26 06:27:43 PM PDT 24 23267852325 ps
T368 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1641612124 Jun 26 06:26:29 PM PDT 24 Jun 26 06:26:31 PM PDT 24 252604035 ps
T369 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3049201980 Jun 26 06:26:15 PM PDT 24 Jun 26 06:26:17 PM PDT 24 124959221 ps
T370 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1241100553 Jun 26 06:26:24 PM PDT 24 Jun 26 06:27:00 PM PDT 24 5136597386 ps
T371 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1431542097 Jun 26 06:26:48 PM PDT 24 Jun 26 06:26:54 PM PDT 24 151353092 ps
T372 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.256295851 Jun 26 06:26:17 PM PDT 24 Jun 26 06:26:21 PM PDT 24 996725131 ps
T373 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.517848105 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:39 PM PDT 24 4780770925 ps
T374 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3332240167 Jun 26 06:26:21 PM PDT 24 Jun 26 06:26:26 PM PDT 24 1078425196 ps
T375 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2335124811 Jun 26 06:26:08 PM PDT 24 Jun 26 06:26:10 PM PDT 24 50116826 ps
T376 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3669729365 Jun 26 06:26:47 PM PDT 24 Jun 26 06:26:55 PM PDT 24 222542893 ps
T377 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1421501726 Jun 26 06:26:07 PM PDT 24 Jun 26 06:26:11 PM PDT 24 2108684730 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3048183112 Jun 26 06:26:17 PM PDT 24 Jun 26 06:26:34 PM PDT 24 5923750157 ps
T102 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4032462199 Jun 26 06:26:17 PM PDT 24 Jun 26 06:26:42 PM PDT 24 9942248623 ps
T379 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3543010216 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:43 PM PDT 24 3647452898 ps
T380 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.627733502 Jun 26 06:26:46 PM PDT 24 Jun 26 06:26:51 PM PDT 24 947516519 ps
T381 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.246032137 Jun 26 06:26:46 PM PDT 24 Jun 26 06:27:10 PM PDT 24 1709538590 ps
T382 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1691416563 Jun 26 06:26:30 PM PDT 24 Jun 26 06:27:08 PM PDT 24 50364080632 ps
T383 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2135708767 Jun 26 06:26:33 PM PDT 24 Jun 26 06:26:35 PM PDT 24 204505791 ps
T384 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2890413917 Jun 26 06:26:09 PM PDT 24 Jun 26 06:27:20 PM PDT 24 1268606863 ps
T385 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2266924500 Jun 26 06:26:23 PM PDT 24 Jun 26 06:26:28 PM PDT 24 1740605587 ps
T386 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1439932062 Jun 26 06:26:25 PM PDT 24 Jun 26 06:26:45 PM PDT 24 13754298559 ps
T387 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3078602418 Jun 26 06:26:45 PM PDT 24 Jun 26 06:26:49 PM PDT 24 168943475 ps
T388 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3853732871 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:42 PM PDT 24 6538756533 ps
T389 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.134503761 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:36 PM PDT 24 218079931 ps
T390 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2245254425 Jun 26 06:26:40 PM PDT 24 Jun 26 06:26:46 PM PDT 24 103265323 ps
T391 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.792170964 Jun 26 06:26:30 PM PDT 24 Jun 26 06:26:40 PM PDT 24 11965826700 ps
T392 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2797875830 Jun 26 06:26:10 PM PDT 24 Jun 26 06:26:12 PM PDT 24 237919866 ps
T393 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.604925495 Jun 26 06:26:39 PM PDT 24 Jun 26 06:26:42 PM PDT 24 173295114 ps
T394 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.833817982 Jun 26 06:26:19 PM PDT 24 Jun 26 06:26:24 PM PDT 24 91767083 ps
T395 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3010607487 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:39 PM PDT 24 759578878 ps
T396 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1001548642 Jun 26 06:26:26 PM PDT 24 Jun 26 06:26:32 PM PDT 24 486251677 ps
T397 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.871914381 Jun 26 06:26:20 PM PDT 24 Jun 26 06:29:26 PM PDT 24 75400456781 ps
T398 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3548797496 Jun 26 06:26:49 PM PDT 24 Jun 26 06:26:56 PM PDT 24 4431524530 ps
T399 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.99293490 Jun 26 06:26:15 PM PDT 24 Jun 26 06:26:30 PM PDT 24 5054415489 ps
T400 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1613292943 Jun 26 06:26:09 PM PDT 24 Jun 26 06:26:11 PM PDT 24 86626661 ps
T401 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1930949218 Jun 26 06:26:23 PM PDT 24 Jun 26 06:26:36 PM PDT 24 4393980975 ps
T402 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3747682668 Jun 26 06:26:38 PM PDT 24 Jun 26 06:26:44 PM PDT 24 298926044 ps
T403 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1562278237 Jun 26 06:26:33 PM PDT 24 Jun 26 06:26:44 PM PDT 24 3943176973 ps
T404 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1426242114 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:46 PM PDT 24 9672653271 ps
T405 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.800765987 Jun 26 06:26:32 PM PDT 24 Jun 26 06:26:41 PM PDT 24 168442729 ps
T406 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2460630410 Jun 26 06:26:17 PM PDT 24 Jun 26 06:26:50 PM PDT 24 6325914909 ps
T407 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1147883378 Jun 26 06:26:25 PM PDT 24 Jun 26 06:26:30 PM PDT 24 2108093764 ps
T408 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3183969562 Jun 26 06:26:36 PM PDT 24 Jun 26 06:26:38 PM PDT 24 174953872 ps
T409 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.494030039 Jun 26 06:26:39 PM PDT 24 Jun 26 06:27:49 PM PDT 24 32639321163 ps
T410 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.153205673 Jun 26 06:26:32 PM PDT 24 Jun 26 06:26:36 PM PDT 24 1550450264 ps
T411 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.948868317 Jun 26 06:26:31 PM PDT 24 Jun 26 06:26:37 PM PDT 24 342110393 ps
T412 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3492581960 Jun 26 06:26:26 PM PDT 24 Jun 26 06:26:30 PM PDT 24 157757313 ps
T413 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.446617226 Jun 26 06:26:34 PM PDT 24 Jun 26 06:26:38 PM PDT 24 151147020 ps
T414 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3109674243 Jun 26 06:26:26 PM PDT 24 Jun 26 06:26:31 PM PDT 24 898017778 ps
T415 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.451864634 Jun 26 06:26:39 PM PDT 24 Jun 26 06:27:01 PM PDT 24 27135818596 ps
T416 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1563241479 Jun 26 06:26:45 PM PDT 24 Jun 26 06:26:53 PM PDT 24 4396723465 ps
T417 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.796283668 Jun 26 06:26:40 PM PDT 24 Jun 26 06:26:45 PM PDT 24 855538549 ps
T418 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.914484788 Jun 26 06:26:16 PM PDT 24 Jun 26 06:27:49 PM PDT 24 64304884219 ps
T419 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.283520135 Jun 26 06:26:24 PM PDT 24 Jun 26 06:26:28 PM PDT 24 810996906 ps
T420 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2705573499 Jun 26 06:26:37 PM PDT 24 Jun 26 06:26:44 PM PDT 24 257618017 ps
T421 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2867064939 Jun 26 06:26:20 PM PDT 24 Jun 26 06:26:22 PM PDT 24 546795813 ps
T422 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3902390663 Jun 26 06:26:38 PM PDT 24 Jun 26 06:26:43 PM PDT 24 203728191 ps
T423 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.735675736 Jun 26 06:26:08 PM PDT 24 Jun 26 06:26:31 PM PDT 24 7574877878 ps
T424 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.84782241 Jun 26 06:26:10 PM PDT 24 Jun 26 06:26:13 PM PDT 24 281437828 ps
T425 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2680163666 Jun 26 06:26:20 PM PDT 24 Jun 26 06:26:23 PM PDT 24 425517163 ps
T426 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4189008943 Jun 26 06:26:45 PM PDT 24 Jun 26 06:27:05 PM PDT 24 6077932526 ps
T427 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.50209071 Jun 26 06:26:08 PM PDT 24 Jun 26 06:26:10 PM PDT 24 55177087 ps
T428 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1942803629 Jun 26 06:26:39 PM PDT 24 Jun 26 06:26:44 PM PDT 24 167703560 ps
T429 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3523690128 Jun 26 06:26:43 PM PDT 24 Jun 26 06:27:03 PM PDT 24 18665135631 ps
T430 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.573860880 Jun 26 06:26:09 PM PDT 24 Jun 26 06:26:21 PM PDT 24 5403109722 ps
T118 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2723009784 Jun 26 06:26:15 PM PDT 24 Jun 26 06:27:33 PM PDT 24 10626291697 ps
T431 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2615289926 Jun 26 06:26:46 PM PDT 24 Jun 26 06:26:50 PM PDT 24 289573824 ps
T432 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3060352498 Jun 26 06:26:41 PM PDT 24 Jun 26 06:26:46 PM PDT 24 1498305461 ps

Test location /workspace/coverage/default/40.rv_dm_stress_all.50764893
Short name T4
Test name
Test status
Simulation time 20433929411 ps
CPU time 7.51 seconds
Started Jun 26 06:59:09 PM PDT 24
Finished Jun 26 06:59:18 PM PDT 24
Peak memory 205176 kb
Host smart-0ba44aad-38d5-4de4-ba20-6545ac0adfd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50764893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.50764893
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1052258379
Short name T25
Test name
Test status
Simulation time 5349916237 ps
CPU time 13.91 seconds
Started Jun 26 06:58:40 PM PDT 24
Finished Jun 26 06:58:56 PM PDT 24
Peak memory 213576 kb
Host smart-3d43bc50-7686-4d55-83ab-32c15b83b0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052258379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1052258379
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3103527744
Short name T66
Test name
Test status
Simulation time 202899459 ps
CPU time 4.55 seconds
Started Jun 26 06:26:08 PM PDT 24
Finished Jun 26 06:26:14 PM PDT 24
Peak memory 213384 kb
Host smart-fdd8213d-3731-4ed5-b661-c9c99f6df778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103527744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3103527744
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3578434424
Short name T73
Test name
Test status
Simulation time 162260882 ps
CPU time 0.85 seconds
Started Jun 26 06:59:05 PM PDT 24
Finished Jun 26 06:59:08 PM PDT 24
Peak memory 204992 kb
Host smart-58e1cbd2-172b-48c8-84cf-fe9c9b9dd145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578434424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3578434424
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1376006166
Short name T79
Test name
Test status
Simulation time 1801177692 ps
CPU time 19.02 seconds
Started Jun 26 06:26:22 PM PDT 24
Finished Jun 26 06:26:43 PM PDT 24
Peak memory 213376 kb
Host smart-828e5b65-8f1c-44f6-a200-36cccbcb8a26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376006166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1376006166
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3692034912
Short name T27
Test name
Test status
Simulation time 7296033993 ps
CPU time 21.7 seconds
Started Jun 26 06:58:17 PM PDT 24
Finished Jun 26 06:58:42 PM PDT 24
Peak memory 205304 kb
Host smart-187abe79-474a-4148-86ae-0193a78a2964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692034912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3692034912
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.136833708
Short name T30
Test name
Test status
Simulation time 9370061295 ps
CPU time 13.09 seconds
Started Jun 26 06:58:45 PM PDT 24
Finished Jun 26 06:58:59 PM PDT 24
Peak memory 213312 kb
Host smart-cc3129f1-193a-455d-8803-f8a4d916bfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136833708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.136833708
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.2793448561
Short name T11
Test name
Test status
Simulation time 7037983129 ps
CPU time 7.05 seconds
Started Jun 26 06:58:55 PM PDT 24
Finished Jun 26 06:59:05 PM PDT 24
Peak memory 205292 kb
Host smart-26199c4b-7f3b-42e0-9134-0e678a83d052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793448561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2793448561
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2345874088
Short name T96
Test name
Test status
Simulation time 7395921743 ps
CPU time 57.96 seconds
Started Jun 26 06:26:17 PM PDT 24
Finished Jun 26 06:27:16 PM PDT 24
Peak memory 205212 kb
Host smart-77af767d-8d88-486e-9e0a-5933aad2702d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345874088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2345874088
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3418551894
Short name T18
Test name
Test status
Simulation time 1084196904 ps
CPU time 1.42 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 06:58:23 PM PDT 24
Peak memory 204968 kb
Host smart-7d3decce-6220-400b-9938-5eb6151366dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418551894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3418551894
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2647689927
Short name T37
Test name
Test status
Simulation time 96195451 ps
CPU time 0.83 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:25 PM PDT 24
Peak memory 214712 kb
Host smart-8df7618f-a27a-4c4a-9ecd-1d0dd9450f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647689927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2647689927
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2183143623
Short name T58
Test name
Test status
Simulation time 492341598 ps
CPU time 1.24 seconds
Started Jun 26 06:58:15 PM PDT 24
Finished Jun 26 06:58:19 PM PDT 24
Peak memory 237456 kb
Host smart-e0b42faa-f742-4021-867a-bc5f5ac88edb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183143623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2183143623
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3691889058
Short name T105
Test name
Test status
Simulation time 94115402 ps
CPU time 2.42 seconds
Started Jun 26 06:26:23 PM PDT 24
Finished Jun 26 06:26:27 PM PDT 24
Peak memory 213296 kb
Host smart-14c6a575-ca20-4aee-9f92-1efe04ca1cde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691889058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3691889058
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.3842397648
Short name T21
Test name
Test status
Simulation time 4306563281 ps
CPU time 7.6 seconds
Started Jun 26 06:59:03 PM PDT 24
Finished Jun 26 06:59:12 PM PDT 24
Peak memory 205316 kb
Host smart-2b854418-5639-4443-a670-6432aa04a4d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842397648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3842397648
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1106498037
Short name T14
Test name
Test status
Simulation time 2690895248 ps
CPU time 4.95 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:59:00 PM PDT 24
Peak memory 205232 kb
Host smart-9e5b1c77-44fc-49aa-af69-bc822c013c78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106498037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1106498037
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.869737511
Short name T16
Test name
Test status
Simulation time 7897994549 ps
CPU time 21.84 seconds
Started Jun 26 06:58:21 PM PDT 24
Finished Jun 26 06:58:47 PM PDT 24
Peak memory 205196 kb
Host smart-7a6de3f7-8127-48a9-a969-20a278b24d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869737511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.869737511
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3544804709
Short name T52
Test name
Test status
Simulation time 214739439 ps
CPU time 0.86 seconds
Started Jun 26 06:58:16 PM PDT 24
Finished Jun 26 06:58:20 PM PDT 24
Peak memory 204948 kb
Host smart-871de700-2d2a-4633-8dda-271615b0de25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544804709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3544804709
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2693272694
Short name T51
Test name
Test status
Simulation time 156725662 ps
CPU time 1.18 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:24 PM PDT 24
Peak memory 215776 kb
Host smart-ca7bfcaf-a79e-46e5-b278-24145b697747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693272694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2693272694
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1880305259
Short name T40
Test name
Test status
Simulation time 3380736580 ps
CPU time 9.82 seconds
Started Jun 26 06:58:16 PM PDT 24
Finished Jun 26 06:58:28 PM PDT 24
Peak memory 205404 kb
Host smart-83caeef0-23b2-49f7-b150-c644869a8397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880305259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1880305259
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2394785814
Short name T140
Test name
Test status
Simulation time 2905674019 ps
CPU time 18.84 seconds
Started Jun 26 06:26:30 PM PDT 24
Finished Jun 26 06:26:51 PM PDT 24
Peak memory 213508 kb
Host smart-08ef0577-da2e-414f-9e26-f18a8123d42b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394785814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2394785814
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.519116702
Short name T135
Test name
Test status
Simulation time 2329851630 ps
CPU time 12.08 seconds
Started Jun 26 06:26:44 PM PDT 24
Finished Jun 26 06:26:58 PM PDT 24
Peak memory 213492 kb
Host smart-8668bfb4-7d40-4930-977f-8918dc51bc90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519116702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.519116702
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3210169743
Short name T38
Test name
Test status
Simulation time 63017417 ps
CPU time 0.85 seconds
Started Jun 26 06:58:29 PM PDT 24
Finished Jun 26 06:58:32 PM PDT 24
Peak memory 205016 kb
Host smart-3486f504-ff1e-4a4f-ad15-d2d5e5a0ee61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210169743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3210169743
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2400414428
Short name T62
Test name
Test status
Simulation time 681632700 ps
CPU time 1.54 seconds
Started Jun 26 06:26:09 PM PDT 24
Finished Jun 26 06:26:12 PM PDT 24
Peak memory 204772 kb
Host smart-0968845b-84eb-4ded-b745-7661f848e495
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400414428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2400414428
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2315499490
Short name T56
Test name
Test status
Simulation time 195483927 ps
CPU time 1 seconds
Started Jun 26 06:58:16 PM PDT 24
Finished Jun 26 06:58:20 PM PDT 24
Peak memory 204952 kb
Host smart-8423d556-d4dd-453c-8a97-9975c9f58063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315499490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2315499490
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3085919308
Short name T97
Test name
Test status
Simulation time 1687320810 ps
CPU time 7.41 seconds
Started Jun 26 06:26:38 PM PDT 24
Finished Jun 26 06:26:46 PM PDT 24
Peak memory 205188 kb
Host smart-1b33556a-a9a1-4e16-b902-28e76a7dda60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085919308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3085919308
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3734923324
Short name T63
Test name
Test status
Simulation time 4096800832 ps
CPU time 20.75 seconds
Started Jun 26 06:26:17 PM PDT 24
Finished Jun 26 06:26:39 PM PDT 24
Peak memory 213428 kb
Host smart-8c027560-48e2-48af-acbc-884e774cde75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734923324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3734923324
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1465517982
Short name T81
Test name
Test status
Simulation time 2772748740 ps
CPU time 15.59 seconds
Started Jun 26 06:26:39 PM PDT 24
Finished Jun 26 06:26:56 PM PDT 24
Peak memory 213452 kb
Host smart-9abb95ad-089c-43bd-a19b-80afd3e85bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465517982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
465517982
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.278779991
Short name T101
Test name
Test status
Simulation time 6889654335 ps
CPU time 18.04 seconds
Started Jun 26 06:26:06 PM PDT 24
Finished Jun 26 06:26:25 PM PDT 24
Peak memory 205156 kb
Host smart-44f941a7-cbdc-4281-af8b-1135b3ee13f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278779991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.278779991
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.2216741514
Short name T19
Test name
Test status
Simulation time 4110352661 ps
CPU time 4.98 seconds
Started Jun 26 06:58:52 PM PDT 24
Finished Jun 26 06:58:59 PM PDT 24
Peak memory 205240 kb
Host smart-c49d6325-b17a-4a3e-80a6-6c5d14cad8dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216741514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2216741514
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2913527548
Short name T49
Test name
Test status
Simulation time 650560255 ps
CPU time 2.42 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:27 PM PDT 24
Peak memory 204672 kb
Host smart-e163e313-8107-4084-a9d3-3de1da919508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913527548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2913527548
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1962178818
Short name T276
Test name
Test status
Simulation time 15342521390 ps
CPU time 42.5 seconds
Started Jun 26 06:58:45 PM PDT 24
Finished Jun 26 06:59:29 PM PDT 24
Peak memory 213624 kb
Host smart-92bb5bc6-79fd-4fc5-bacd-56c99764effc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962178818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1962178818
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2890413917
Short name T384
Test name
Test status
Simulation time 1268606863 ps
CPU time 69.71 seconds
Started Jun 26 06:26:09 PM PDT 24
Finished Jun 26 06:27:20 PM PDT 24
Peak memory 213216 kb
Host smart-121b05e8-be02-4e0f-ac76-26ed79335611
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890413917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2890413917
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2167506342
Short name T94
Test name
Test status
Simulation time 4011972466 ps
CPU time 26.84 seconds
Started Jun 26 06:26:08 PM PDT 24
Finished Jun 26 06:26:37 PM PDT 24
Peak memory 213396 kb
Host smart-4d0c8365-25a6-443f-9011-e36fab338d11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167506342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2167506342
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2660860739
Short name T92
Test name
Test status
Simulation time 274863070 ps
CPU time 2.86 seconds
Started Jun 26 06:26:07 PM PDT 24
Finished Jun 26 06:26:11 PM PDT 24
Peak memory 214348 kb
Host smart-5a2442f0-a0ce-498d-a5ab-c31b5aadc515
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660860739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2660860739
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1599428015
Short name T128
Test name
Test status
Simulation time 1984149294 ps
CPU time 4.42 seconds
Started Jun 26 06:26:10 PM PDT 24
Finished Jun 26 06:26:16 PM PDT 24
Peak memory 218608 kb
Host smart-e5536aef-70fa-46a0-8e14-d27815a87f8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599428015 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1599428015
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.4212614597
Short name T126
Test name
Test status
Simulation time 185834495 ps
CPU time 2.02 seconds
Started Jun 26 06:26:09 PM PDT 24
Finished Jun 26 06:26:13 PM PDT 24
Peak memory 213520 kb
Host smart-bc0eadbd-1818-4d4a-a95d-5a35cbe36d5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212614597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.4212614597
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1604053636
Short name T353
Test name
Test status
Simulation time 100117999914 ps
CPU time 140.2 seconds
Started Jun 26 06:26:10 PM PDT 24
Finished Jun 26 06:28:31 PM PDT 24
Peak memory 205004 kb
Host smart-3a2f88bc-b5cd-4b73-9183-ed835f4be4e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604053636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1604053636
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.856525751
Short name T310
Test name
Test status
Simulation time 57488575151 ps
CPU time 77.81 seconds
Started Jun 26 06:26:08 PM PDT 24
Finished Jun 26 06:27:28 PM PDT 24
Peak memory 205052 kb
Host smart-98685272-b683-4f95-8aec-c5baecbb078d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856525751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
v_dm_jtag_dmi_csr_bit_bash.856525751
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.824766301
Short name T316
Test name
Test status
Simulation time 6063981919 ps
CPU time 5.83 seconds
Started Jun 26 06:26:10 PM PDT 24
Finished Jun 26 06:26:17 PM PDT 24
Peak memory 205064 kb
Host smart-33adf248-dcb0-484c-946a-5f0f86f3574b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824766301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.824766301
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.573860880
Short name T430
Test name
Test status
Simulation time 5403109722 ps
CPU time 10.69 seconds
Started Jun 26 06:26:09 PM PDT 24
Finished Jun 26 06:26:21 PM PDT 24
Peak memory 204944 kb
Host smart-792fd98c-cfd6-47f8-a589-048370834e1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573860880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.573860880
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.746130782
Short name T308
Test name
Test status
Simulation time 312734250 ps
CPU time 0.9 seconds
Started Jun 26 06:26:11 PM PDT 24
Finished Jun 26 06:26:13 PM PDT 24
Peak memory 204792 kb
Host smart-16b8f245-25c7-4632-9795-0388201236f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746130782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.746130782
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1689234704
Short name T319
Test name
Test status
Simulation time 50895010899 ps
CPU time 120.01 seconds
Started Jun 26 06:26:09 PM PDT 24
Finished Jun 26 06:28:11 PM PDT 24
Peak memory 205092 kb
Host smart-28689a13-049e-4223-b349-f13de3c857fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689234704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1689234704
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.84782241
Short name T424
Test name
Test status
Simulation time 281437828 ps
CPU time 1.41 seconds
Started Jun 26 06:26:10 PM PDT 24
Finished Jun 26 06:26:13 PM PDT 24
Peak memory 204700 kb
Host smart-9c879d88-8d38-4a44-9229-bbc056590aeb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84782241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.84782241
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.50209071
Short name T427
Test name
Test status
Simulation time 55177087 ps
CPU time 0.74 seconds
Started Jun 26 06:26:08 PM PDT 24
Finished Jun 26 06:26:10 PM PDT 24
Peak memory 204832 kb
Host smart-7919648e-bf79-4f5d-b82f-496065e29b3d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50209071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_parti
al_access.50209071
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1613292943
Short name T400
Test name
Test status
Simulation time 86626661 ps
CPU time 0.76 seconds
Started Jun 26 06:26:09 PM PDT 24
Finished Jun 26 06:26:11 PM PDT 24
Peak memory 204788 kb
Host smart-dddb9d87-f53b-4914-993e-cbbaaccdbce3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613292943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1613292943
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3661258981
Short name T106
Test name
Test status
Simulation time 306756729 ps
CPU time 3.48 seconds
Started Jun 26 06:26:09 PM PDT 24
Finished Jun 26 06:26:14 PM PDT 24
Peak memory 205184 kb
Host smart-8838ab45-b84e-4517-9cf3-ecfa54daec5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661258981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3661258981
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1988698992
Short name T137
Test name
Test status
Simulation time 5456473028 ps
CPU time 31.46 seconds
Started Jun 26 06:26:07 PM PDT 24
Finished Jun 26 06:26:40 PM PDT 24
Peak memory 213420 kb
Host smart-6017e1c2-0b4b-4192-8d2e-b84d096d6376
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988698992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1988698992
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.807726249
Short name T115
Test name
Test status
Simulation time 9123866375 ps
CPU time 77.07 seconds
Started Jun 26 06:26:07 PM PDT 24
Finished Jun 26 06:27:24 PM PDT 24
Peak memory 213456 kb
Host smart-6c3ee275-519f-410f-b71e-a60eb1df77a1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807726249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.807726249
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3205128593
Short name T324
Test name
Test status
Simulation time 261804469 ps
CPU time 2.63 seconds
Started Jun 26 06:26:07 PM PDT 24
Finished Jun 26 06:26:10 PM PDT 24
Peak memory 213432 kb
Host smart-c6e1f218-2cfe-4ae8-a909-d60d95b85cb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205128593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3205128593
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1086887297
Short name T99
Test name
Test status
Simulation time 2385659226 ps
CPU time 5.47 seconds
Started Jun 26 06:26:16 PM PDT 24
Finished Jun 26 06:26:23 PM PDT 24
Peak memory 220632 kb
Host smart-461f24a9-8dd2-4349-86fe-0ff53a3ebccb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086887297 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1086887297
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3958676128
Short name T95
Test name
Test status
Simulation time 630290419 ps
CPU time 2.43 seconds
Started Jun 26 06:26:11 PM PDT 24
Finished Jun 26 06:26:15 PM PDT 24
Peak memory 213320 kb
Host smart-af6316e0-4cb5-467f-8fa2-c1155e7bb324
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958676128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3958676128
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4206265883
Short name T355
Test name
Test status
Simulation time 34038988022 ps
CPU time 100.55 seconds
Started Jun 26 06:26:09 PM PDT 24
Finished Jun 26 06:27:51 PM PDT 24
Peak memory 205024 kb
Host smart-91c21a91-38d2-452d-a213-da85e8ff613d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206265883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.4206265883
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3552994753
Short name T363
Test name
Test status
Simulation time 34965251462 ps
CPU time 15.46 seconds
Started Jun 26 06:26:10 PM PDT 24
Finished Jun 26 06:26:27 PM PDT 24
Peak memory 204968 kb
Host smart-92e55ac2-85da-40ac-8579-8346c6495525
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552994753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3552994753
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1244158910
Short name T312
Test name
Test status
Simulation time 4780255486 ps
CPU time 5.54 seconds
Started Jun 26 06:26:06 PM PDT 24
Finished Jun 26 06:26:12 PM PDT 24
Peak memory 205024 kb
Host smart-bdd7d67a-1c44-4dc1-a72d-b924c3fe554e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244158910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
244158910
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1421501726
Short name T377
Test name
Test status
Simulation time 2108684730 ps
CPU time 2.83 seconds
Started Jun 26 06:26:07 PM PDT 24
Finished Jun 26 06:26:11 PM PDT 24
Peak memory 204768 kb
Host smart-cc637066-8916-4799-b03f-737e5529e5af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421501726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1421501726
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.735675736
Short name T423
Test name
Test status
Simulation time 7574877878 ps
CPU time 21.38 seconds
Started Jun 26 06:26:08 PM PDT 24
Finished Jun 26 06:26:31 PM PDT 24
Peak memory 205040 kb
Host smart-f85716b2-7f99-4741-a1de-a823adc461eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735675736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.735675736
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2797875830
Short name T392
Test name
Test status
Simulation time 237919866 ps
CPU time 1.03 seconds
Started Jun 26 06:26:10 PM PDT 24
Finished Jun 26 06:26:12 PM PDT 24
Peak memory 204760 kb
Host smart-68e067fd-0d3e-48e9-91fa-7cfc0b9b0031
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797875830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2797875830
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3030726017
Short name T343
Test name
Test status
Simulation time 400745306 ps
CPU time 1.14 seconds
Started Jun 26 06:26:07 PM PDT 24
Finished Jun 26 06:26:10 PM PDT 24
Peak memory 204772 kb
Host smart-d38a2d90-bf5f-4dbf-829f-90da0268674d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030726017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
030726017
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3906811926
Short name T314
Test name
Test status
Simulation time 74952195 ps
CPU time 0.8 seconds
Started Jun 26 06:26:09 PM PDT 24
Finished Jun 26 06:26:11 PM PDT 24
Peak memory 204784 kb
Host smart-fca1e9bc-fae2-41b4-b587-9a88047de6bc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906811926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3906811926
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2335124811
Short name T375
Test name
Test status
Simulation time 50116826 ps
CPU time 0.73 seconds
Started Jun 26 06:26:08 PM PDT 24
Finished Jun 26 06:26:10 PM PDT 24
Peak memory 204752 kb
Host smart-10fadf8c-1772-4da2-8808-43acbf73e2f3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335124811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2335124811
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.416709856
Short name T109
Test name
Test status
Simulation time 863331127 ps
CPU time 6.6 seconds
Started Jun 26 06:26:20 PM PDT 24
Finished Jun 26 06:26:28 PM PDT 24
Peak memory 205184 kb
Host smart-ced0c562-c11c-4239-8456-f9428ff3128c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416709856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.416709856
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1477369328
Short name T334
Test name
Test status
Simulation time 189665384 ps
CPU time 4.92 seconds
Started Jun 26 06:26:08 PM PDT 24
Finished Jun 26 06:26:15 PM PDT 24
Peak memory 213408 kb
Host smart-8b1bdf45-5b71-4127-bc60-5e2be5bef1df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477369328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1477369328
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1272848184
Short name T139
Test name
Test status
Simulation time 2070072373 ps
CPU time 20.29 seconds
Started Jun 26 06:26:08 PM PDT 24
Finished Jun 26 06:26:30 PM PDT 24
Peak memory 213368 kb
Host smart-bfc4ac56-2a0a-4f05-93fa-2de08696a1f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272848184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1272848184
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1987156167
Short name T72
Test name
Test status
Simulation time 517280779 ps
CPU time 4.89 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:37 PM PDT 24
Peak memory 219432 kb
Host smart-e18b8092-6166-409c-9fee-1d98bc19dcae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987156167 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1987156167
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2144132105
Short name T325
Test name
Test status
Simulation time 76616390 ps
CPU time 1.52 seconds
Started Jun 26 06:26:36 PM PDT 24
Finished Jun 26 06:26:39 PM PDT 24
Peak memory 213364 kb
Host smart-a0c8788e-6976-4403-b005-1c0d1271429d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144132105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2144132105
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3236433007
Short name T336
Test name
Test status
Simulation time 47826911561 ps
CPU time 68.15 seconds
Started Jun 26 06:26:32 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 205072 kb
Host smart-75b34172-832f-4906-9241-5f7d2d1fb1e3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236433007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3236433007
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3543010216
Short name T379
Test name
Test status
Simulation time 3647452898 ps
CPU time 11.05 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:43 PM PDT 24
Peak memory 204996 kb
Host smart-fa0cc60d-e79e-49f5-84c2-01d9aa455215
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543010216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3543010216
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1716186096
Short name T298
Test name
Test status
Simulation time 324581393 ps
CPU time 0.93 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:34 PM PDT 24
Peak memory 204768 kb
Host smart-470eab52-5057-4492-9c07-23aadb36ea52
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716186096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1716186096
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2253863302
Short name T112
Test name
Test status
Simulation time 6405527976 ps
CPU time 8.38 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:41 PM PDT 24
Peak memory 205244 kb
Host smart-b1a3bf22-0470-4da2-84fb-fcd32a6d6dae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253863302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2253863302
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2627142742
Short name T134
Test name
Test status
Simulation time 4463338475 ps
CPU time 6.56 seconds
Started Jun 26 06:26:40 PM PDT 24
Finished Jun 26 06:26:48 PM PDT 24
Peak memory 213548 kb
Host smart-c15aeecd-77e8-4cf5-a8b2-7ab58699afa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627142742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2627142742
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1689078464
Short name T82
Test name
Test status
Simulation time 3194822329 ps
CPU time 21.88 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:54 PM PDT 24
Peak memory 214196 kb
Host smart-22f24e2e-d454-4c99-91b9-6088ef84f820
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689078464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
689078464
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3601640504
Short name T311
Test name
Test status
Simulation time 894832795 ps
CPU time 4.36 seconds
Started Jun 26 06:26:28 PM PDT 24
Finished Jun 26 06:26:33 PM PDT 24
Peak memory 219916 kb
Host smart-f8c40bdb-b680-46a7-a199-9881c93880e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601640504 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3601640504
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.576457638
Short name T342
Test name
Test status
Simulation time 154947172 ps
CPU time 2.12 seconds
Started Jun 26 06:26:32 PM PDT 24
Finished Jun 26 06:26:36 PM PDT 24
Peak memory 213312 kb
Host smart-4220d07c-dc4f-4d2c-8466-d30a30a84033
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576457638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.576457638
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3353223685
Short name T354
Test name
Test status
Simulation time 25817111723 ps
CPU time 12.42 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:45 PM PDT 24
Peak memory 205044 kb
Host smart-6c236999-050d-473d-b182-e55d99454a5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353223685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3353223685
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3307119820
Short name T315
Test name
Test status
Simulation time 1553979810 ps
CPU time 1.21 seconds
Started Jun 26 06:26:32 PM PDT 24
Finished Jun 26 06:26:35 PM PDT 24
Peak memory 204972 kb
Host smart-cd32ba06-d1c6-49a6-b59f-cfeb266d111c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307119820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3307119820
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2135708767
Short name T383
Test name
Test status
Simulation time 204505791 ps
CPU time 0.98 seconds
Started Jun 26 06:26:33 PM PDT 24
Finished Jun 26 06:26:35 PM PDT 24
Peak memory 204756 kb
Host smart-fa83920f-0b38-4108-9af6-b977d3dafb40
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135708767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2135708767
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3010607487
Short name T395
Test name
Test status
Simulation time 759578878 ps
CPU time 6.8 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:39 PM PDT 24
Peak memory 205136 kb
Host smart-70e332a4-114b-42c0-9f38-a278c3d8fbaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010607487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3010607487
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.948868317
Short name T411
Test name
Test status
Simulation time 342110393 ps
CPU time 4.96 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:37 PM PDT 24
Peak memory 213360 kb
Host smart-f87c57fe-014f-40e9-ab1f-ed4810902b86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948868317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.948868317
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3019313951
Short name T78
Test name
Test status
Simulation time 1079782288 ps
CPU time 10.07 seconds
Started Jun 26 06:26:29 PM PDT 24
Finished Jun 26 06:26:40 PM PDT 24
Peak memory 213412 kb
Host smart-2a209b92-b22e-4c16-ad7a-4a6ed788d0de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019313951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
019313951
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3597592302
Short name T360
Test name
Test status
Simulation time 297750578 ps
CPU time 4.07 seconds
Started Jun 26 06:26:44 PM PDT 24
Finished Jun 26 06:26:49 PM PDT 24
Peak memory 219860 kb
Host smart-a33725c5-7a28-4f7b-9727-c09077ce532f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597592302 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3597592302
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1421590911
Short name T365
Test name
Test status
Simulation time 158867967 ps
CPU time 1.71 seconds
Started Jun 26 06:26:37 PM PDT 24
Finished Jun 26 06:26:40 PM PDT 24
Peak memory 213340 kb
Host smart-60a00d07-b572-4e45-93bf-15755c188d9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421590911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1421590911
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.494030039
Short name T409
Test name
Test status
Simulation time 32639321163 ps
CPU time 68.98 seconds
Started Jun 26 06:26:39 PM PDT 24
Finished Jun 26 06:27:49 PM PDT 24
Peak memory 205072 kb
Host smart-585c4009-5561-4791-89d3-52680f9e8acd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494030039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rv_dm_jtag_dmi_csr_bit_bash.494030039
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3255866724
Short name T362
Test name
Test status
Simulation time 5154656636 ps
CPU time 7.87 seconds
Started Jun 26 06:26:39 PM PDT 24
Finished Jun 26 06:26:48 PM PDT 24
Peak memory 205036 kb
Host smart-766c2af8-e525-43ca-a484-b5e80fa553ef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255866724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3255866724
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1641612124
Short name T368
Test name
Test status
Simulation time 252604035 ps
CPU time 0.76 seconds
Started Jun 26 06:26:29 PM PDT 24
Finished Jun 26 06:26:31 PM PDT 24
Peak memory 204780 kb
Host smart-3635d465-3eca-408b-8985-36851820625e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641612124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1641612124
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3902390663
Short name T422
Test name
Test status
Simulation time 203728191 ps
CPU time 3.53 seconds
Started Jun 26 06:26:38 PM PDT 24
Finished Jun 26 06:26:43 PM PDT 24
Peak memory 205192 kb
Host smart-35c74a79-1a6a-470a-baf7-607ce9a9e4c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902390663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3902390663
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2705573499
Short name T420
Test name
Test status
Simulation time 257618017 ps
CPU time 5.55 seconds
Started Jun 26 06:26:37 PM PDT 24
Finished Jun 26 06:26:44 PM PDT 24
Peak memory 213396 kb
Host smart-7989b117-5fd4-4feb-a088-911b2f72f39c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705573499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2705573499
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3442083234
Short name T83
Test name
Test status
Simulation time 3184483811 ps
CPU time 6.8 seconds
Started Jun 26 06:26:39 PM PDT 24
Finished Jun 26 06:26:47 PM PDT 24
Peak memory 218484 kb
Host smart-4b889dde-ee7c-46c0-86b6-7bd9a558b7df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442083234 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3442083234
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.434066608
Short name T91
Test name
Test status
Simulation time 51995751 ps
CPU time 1.46 seconds
Started Jun 26 06:26:38 PM PDT 24
Finished Jun 26 06:26:40 PM PDT 24
Peak memory 213300 kb
Host smart-1aef4b34-176d-4c54-8de9-730ba2c9012f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434066608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.434066608
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2859954241
Short name T345
Test name
Test status
Simulation time 36711752 ps
CPU time 0.74 seconds
Started Jun 26 06:26:37 PM PDT 24
Finished Jun 26 06:26:39 PM PDT 24
Peak memory 204992 kb
Host smart-0dcb9a57-4eaa-45dd-8243-0aa25ec51245
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859954241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2859954241
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3303085966
Short name T295
Test name
Test status
Simulation time 1074307206 ps
CPU time 2.33 seconds
Started Jun 26 06:26:40 PM PDT 24
Finished Jun 26 06:26:44 PM PDT 24
Peak memory 204972 kb
Host smart-5b62b30d-61a0-45a5-b575-cb632c69be86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303085966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3303085966
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.796283668
Short name T417
Test name
Test status
Simulation time 855538549 ps
CPU time 2.81 seconds
Started Jun 26 06:26:40 PM PDT 24
Finished Jun 26 06:26:45 PM PDT 24
Peak memory 204792 kb
Host smart-715cf5fb-d486-45b2-89a1-dfd3bdd0e848
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796283668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.796283668
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3747682668
Short name T402
Test name
Test status
Simulation time 298926044 ps
CPU time 4.46 seconds
Started Jun 26 06:26:38 PM PDT 24
Finished Jun 26 06:26:44 PM PDT 24
Peak memory 205176 kb
Host smart-958c998b-0d55-4e44-bf65-49b3ba81b663
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747682668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3747682668
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2245254425
Short name T390
Test name
Test status
Simulation time 103265323 ps
CPU time 4.54 seconds
Started Jun 26 06:26:40 PM PDT 24
Finished Jun 26 06:26:46 PM PDT 24
Peak memory 213400 kb
Host smart-24955ac6-f108-40c4-8ad3-407009f4a33c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245254425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2245254425
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4094818180
Short name T136
Test name
Test status
Simulation time 4177164474 ps
CPU time 12.6 seconds
Started Jun 26 06:26:44 PM PDT 24
Finished Jun 26 06:26:58 PM PDT 24
Peak memory 213528 kb
Host smart-7b6dacac-f747-42b1-845d-cbcccb531a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094818180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.4
094818180
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2229718599
Short name T366
Test name
Test status
Simulation time 921257336 ps
CPU time 4.04 seconds
Started Jun 26 06:26:57 PM PDT 24
Finished Jun 26 06:27:02 PM PDT 24
Peak memory 218912 kb
Host smart-47116759-5b8b-4d2b-9571-6472274a3883
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229718599 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2229718599
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3782417816
Short name T122
Test name
Test status
Simulation time 381198154 ps
CPU time 2.2 seconds
Started Jun 26 06:26:40 PM PDT 24
Finished Jun 26 06:26:44 PM PDT 24
Peak memory 213260 kb
Host smart-7c9c1b59-f531-4597-a86f-06755eeed07d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782417816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3782417816
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.451864634
Short name T415
Test name
Test status
Simulation time 27135818596 ps
CPU time 20.53 seconds
Started Jun 26 06:26:39 PM PDT 24
Finished Jun 26 06:27:01 PM PDT 24
Peak memory 205008 kb
Host smart-8c695678-fdfe-4826-98c8-024fea35faaa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451864634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
rv_dm_jtag_dmi_csr_bit_bash.451864634
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.489136074
Short name T299
Test name
Test status
Simulation time 3365417939 ps
CPU time 1.67 seconds
Started Jun 26 06:26:39 PM PDT 24
Finished Jun 26 06:26:43 PM PDT 24
Peak memory 204860 kb
Host smart-103cad51-960e-4d6a-8977-cf8a161ce8f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489136074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.489136074
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.501968727
Short name T297
Test name
Test status
Simulation time 944605575 ps
CPU time 1.45 seconds
Started Jun 26 06:26:44 PM PDT 24
Finished Jun 26 06:26:47 PM PDT 24
Peak memory 204788 kb
Host smart-7bb55b22-e2fb-4c1f-8c6f-3da797d04b51
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501968727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.501968727
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2184322687
Short name T93
Test name
Test status
Simulation time 1663300573 ps
CPU time 7.65 seconds
Started Jun 26 06:26:40 PM PDT 24
Finished Jun 26 06:26:49 PM PDT 24
Peak memory 205240 kb
Host smart-0ee271d8-1948-44ea-ae4d-899fb91b5c54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184322687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2184322687
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.809407905
Short name T85
Test name
Test status
Simulation time 80087587 ps
CPU time 2.16 seconds
Started Jun 26 06:26:38 PM PDT 24
Finished Jun 26 06:26:42 PM PDT 24
Peak memory 213352 kb
Host smart-9f2ce09a-ffc3-4eb8-8240-e1227c697293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809407905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.809407905
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.57182489
Short name T80
Test name
Test status
Simulation time 1804020580 ps
CPU time 22.74 seconds
Started Jun 26 06:26:38 PM PDT 24
Finished Jun 26 06:27:02 PM PDT 24
Peak memory 213424 kb
Host smart-57611082-eb3c-4d7a-a565-187cfd9f718e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57182489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.57182489
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3060352498
Short name T432
Test name
Test status
Simulation time 1498305461 ps
CPU time 3.79 seconds
Started Jun 26 06:26:41 PM PDT 24
Finished Jun 26 06:26:46 PM PDT 24
Peak memory 213416 kb
Host smart-46f5760a-7492-42aa-88ae-98ab4466e6c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060352498 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3060352498
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.604925495
Short name T393
Test name
Test status
Simulation time 173295114 ps
CPU time 1.42 seconds
Started Jun 26 06:26:39 PM PDT 24
Finished Jun 26 06:26:42 PM PDT 24
Peak memory 213152 kb
Host smart-14e05550-9862-4fae-9945-4fd53f133c37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604925495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.604925495
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3523690128
Short name T429
Test name
Test status
Simulation time 18665135631 ps
CPU time 18.77 seconds
Started Jun 26 06:26:43 PM PDT 24
Finished Jun 26 06:27:03 PM PDT 24
Peak memory 205084 kb
Host smart-281762e5-f1ba-42f5-872d-a1d01b72cec3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523690128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3523690128
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2147438158
Short name T318
Test name
Test status
Simulation time 4750130965 ps
CPU time 12.85 seconds
Started Jun 26 06:26:44 PM PDT 24
Finished Jun 26 06:26:58 PM PDT 24
Peak memory 205060 kb
Host smart-9d554e71-2c67-40e6-9bd1-f08352148c44
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147438158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2147438158
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2367699497
Short name T307
Test name
Test status
Simulation time 199347664 ps
CPU time 1.02 seconds
Started Jun 26 06:26:37 PM PDT 24
Finished Jun 26 06:26:39 PM PDT 24
Peak memory 204756 kb
Host smart-b8783c93-7552-46b1-b9f3-cdce756536ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367699497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2367699497
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1942803629
Short name T428
Test name
Test status
Simulation time 167703560 ps
CPU time 2.9 seconds
Started Jun 26 06:26:39 PM PDT 24
Finished Jun 26 06:26:44 PM PDT 24
Peak memory 215956 kb
Host smart-f6427318-72e8-4375-85f5-8bda240a2e5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942803629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1942803629
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2479134944
Short name T138
Test name
Test status
Simulation time 2243380014 ps
CPU time 19.4 seconds
Started Jun 26 06:26:39 PM PDT 24
Finished Jun 26 06:27:00 PM PDT 24
Peak memory 213468 kb
Host smart-966cd91d-4e79-4321-9424-44619bb9e6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479134944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
479134944
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3078602418
Short name T387
Test name
Test status
Simulation time 168943475 ps
CPU time 2.41 seconds
Started Jun 26 06:26:45 PM PDT 24
Finished Jun 26 06:26:49 PM PDT 24
Peak memory 217540 kb
Host smart-faf18d2e-d8cb-4412-a9ad-7e57a58432e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078602418 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3078602418
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.648783527
Short name T127
Test name
Test status
Simulation time 442738185 ps
CPU time 2.41 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:26:53 PM PDT 24
Peak memory 213336 kb
Host smart-c6789128-7b96-4084-9884-a25cfbb3ba7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648783527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.648783527
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2890976637
Short name T323
Test name
Test status
Simulation time 32993067123 ps
CPU time 23.26 seconds
Started Jun 26 06:26:38 PM PDT 24
Finished Jun 26 06:27:03 PM PDT 24
Peak memory 205056 kb
Host smart-54098050-f170-4b1a-bd22-2c47bf332368
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890976637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2890976637
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3077844111
Short name T352
Test name
Test status
Simulation time 1910283057 ps
CPU time 1.96 seconds
Started Jun 26 06:26:39 PM PDT 24
Finished Jun 26 06:26:42 PM PDT 24
Peak memory 204912 kb
Host smart-6124f135-123e-4391-a3d8-770464670ad6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077844111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3077844111
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3183969562
Short name T408
Test name
Test status
Simulation time 174953872 ps
CPU time 1.12 seconds
Started Jun 26 06:26:36 PM PDT 24
Finished Jun 26 06:26:38 PM PDT 24
Peak memory 204680 kb
Host smart-2c035449-b65d-4e55-8981-d9a484f309d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183969562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3183969562
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3506735842
Short name T121
Test name
Test status
Simulation time 202239669 ps
CPU time 3.83 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:26:54 PM PDT 24
Peak memory 205172 kb
Host smart-9a5c5cdc-1728-4652-9e12-562e6db73cf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506735842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3506735842
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2182059743
Short name T322
Test name
Test status
Simulation time 1883246923 ps
CPU time 4.21 seconds
Started Jun 26 06:26:39 PM PDT 24
Finished Jun 26 06:26:44 PM PDT 24
Peak memory 213480 kb
Host smart-216a842f-92d5-4bb9-a509-cf00fc0c8875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182059743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2182059743
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1563241479
Short name T416
Test name
Test status
Simulation time 4396723465 ps
CPU time 5.71 seconds
Started Jun 26 06:26:45 PM PDT 24
Finished Jun 26 06:26:53 PM PDT 24
Peak memory 220148 kb
Host smart-20025172-0906-4ffc-8d4e-65d300bd23ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563241479 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1563241479
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4184364118
Short name T327
Test name
Test status
Simulation time 146899942 ps
CPU time 2.5 seconds
Started Jun 26 06:26:44 PM PDT 24
Finished Jun 26 06:26:48 PM PDT 24
Peak memory 213324 kb
Host smart-0f94984d-712c-4c06-9f22-dbb3b9b54cca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184364118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.4184364118
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1081534486
Short name T303
Test name
Test status
Simulation time 22333575752 ps
CPU time 18.8 seconds
Started Jun 26 06:26:46 PM PDT 24
Finished Jun 26 06:27:06 PM PDT 24
Peak memory 205056 kb
Host smart-eb571c45-d611-498f-85d1-cd720b4e684d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081534486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.1081534486
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.627733502
Short name T380
Test name
Test status
Simulation time 947516519 ps
CPU time 2.54 seconds
Started Jun 26 06:26:46 PM PDT 24
Finished Jun 26 06:26:51 PM PDT 24
Peak memory 204980 kb
Host smart-244fdda2-0851-42bc-ad8a-0b1e7a4cb5f9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627733502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.627733502
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.85240084
Short name T358
Test name
Test status
Simulation time 394230052 ps
CPU time 0.98 seconds
Started Jun 26 06:26:46 PM PDT 24
Finished Jun 26 06:26:49 PM PDT 24
Peak memory 204772 kb
Host smart-96ca4ea9-dbdb-4de4-a346-287eb35458fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85240084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.85240084
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3669729365
Short name T376
Test name
Test status
Simulation time 222542893 ps
CPU time 6.33 seconds
Started Jun 26 06:26:47 PM PDT 24
Finished Jun 26 06:26:55 PM PDT 24
Peak memory 205104 kb
Host smart-91b0ee55-81e6-4196-a4d5-886a645acf8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669729365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3669729365
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1431542097
Short name T371
Test name
Test status
Simulation time 151353092 ps
CPU time 4.33 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:26:54 PM PDT 24
Peak memory 213356 kb
Host smart-aca89ea9-a19e-4f28-b3c5-26cfe96b9e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431542097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1431542097
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2627531898
Short name T84
Test name
Test status
Simulation time 1506921581 ps
CPU time 9.15 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 213368 kb
Host smart-f71ebbba-be57-4329-9776-da178041d53c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627531898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
627531898
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3548797496
Short name T398
Test name
Test status
Simulation time 4431524530 ps
CPU time 5.52 seconds
Started Jun 26 06:26:49 PM PDT 24
Finished Jun 26 06:26:56 PM PDT 24
Peak memory 213556 kb
Host smart-36b72ebc-b30b-4cf7-94cc-170e71fa106d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548797496 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3548797496
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.657455171
Short name T113
Test name
Test status
Simulation time 221943169 ps
CPU time 1.69 seconds
Started Jun 26 06:26:45 PM PDT 24
Finished Jun 26 06:26:48 PM PDT 24
Peak memory 213324 kb
Host smart-bbd68609-e5de-49c1-a47e-30468bde15fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657455171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.657455171
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2398963370
Short name T306
Test name
Test status
Simulation time 9558195228 ps
CPU time 11.26 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:27:01 PM PDT 24
Peak memory 205052 kb
Host smart-9ad9036f-82cc-4088-9d84-df1c3470e2dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398963370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2398963370
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3898473443
Short name T321
Test name
Test status
Simulation time 2808895688 ps
CPU time 7.74 seconds
Started Jun 26 06:26:50 PM PDT 24
Finished Jun 26 06:26:59 PM PDT 24
Peak memory 205064 kb
Host smart-393d8948-d75c-402d-a4bf-775fd2b8f797
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898473443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3898473443
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2145615628
Short name T317
Test name
Test status
Simulation time 250597338 ps
CPU time 0.89 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:26:50 PM PDT 24
Peak memory 204784 kb
Host smart-24b91e04-9f80-4310-b7ec-ce79bac961ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145615628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2145615628
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3389721604
Short name T349
Test name
Test status
Simulation time 102869194 ps
CPU time 3.75 seconds
Started Jun 26 06:26:45 PM PDT 24
Finished Jun 26 06:26:50 PM PDT 24
Peak memory 205196 kb
Host smart-84e0432d-aef4-4e57-9ec2-3817ae256682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389721604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3389721604
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2349034515
Short name T326
Test name
Test status
Simulation time 213094512 ps
CPU time 4.48 seconds
Started Jun 26 06:26:46 PM PDT 24
Finished Jun 26 06:26:52 PM PDT 24
Peak memory 213412 kb
Host smart-08290305-a3ec-4fd3-80ed-59f6ded5fcca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349034515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2349034515
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4189008943
Short name T426
Test name
Test status
Simulation time 6077932526 ps
CPU time 18.66 seconds
Started Jun 26 06:26:45 PM PDT 24
Finished Jun 26 06:27:05 PM PDT 24
Peak memory 213440 kb
Host smart-5b1e38c1-adce-4ed3-a88e-c0e0def6a09c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189008943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4
189008943
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2615289926
Short name T431
Test name
Test status
Simulation time 289573824 ps
CPU time 2.78 seconds
Started Jun 26 06:26:46 PM PDT 24
Finished Jun 26 06:26:50 PM PDT 24
Peak memory 213368 kb
Host smart-90ef9a80-9e30-470f-92dc-07fefa9c03bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615289926 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2615289926
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1723521098
Short name T114
Test name
Test status
Simulation time 503865620 ps
CPU time 2.84 seconds
Started Jun 26 06:26:45 PM PDT 24
Finished Jun 26 06:26:50 PM PDT 24
Peak memory 213236 kb
Host smart-70bc01a9-b6c6-46e2-b973-df3028c92f72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723521098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1723521098
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.769313414
Short name T341
Test name
Test status
Simulation time 24180005616 ps
CPU time 19.45 seconds
Started Jun 26 06:26:47 PM PDT 24
Finished Jun 26 06:27:08 PM PDT 24
Peak memory 205068 kb
Host smart-1ed05e9f-a7b1-48c4-a31b-2a952f467bb2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769313414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.769313414
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4115604182
Short name T331
Test name
Test status
Simulation time 1503050683 ps
CPU time 4.71 seconds
Started Jun 26 06:26:47 PM PDT 24
Finished Jun 26 06:26:53 PM PDT 24
Peak memory 204996 kb
Host smart-aeab0848-178a-4b2b-9b89-3be6a8509058
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115604182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
4115604182
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1662595050
Short name T300
Test name
Test status
Simulation time 100128758 ps
CPU time 0.91 seconds
Started Jun 26 06:26:46 PM PDT 24
Finished Jun 26 06:26:48 PM PDT 24
Peak memory 204776 kb
Host smart-ad80ed69-24b6-47f1-9e02-72cdae8d03b5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662595050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1662595050
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3287280620
Short name T346
Test name
Test status
Simulation time 236556391 ps
CPU time 3.64 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:26:54 PM PDT 24
Peak memory 205116 kb
Host smart-ee9e852c-5c70-4278-8925-04ef00213371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287280620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3287280620
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2787876057
Short name T348
Test name
Test status
Simulation time 600109323 ps
CPU time 6.02 seconds
Started Jun 26 06:26:48 PM PDT 24
Finished Jun 26 06:26:56 PM PDT 24
Peak memory 213488 kb
Host smart-e4e21b4b-6703-482c-acec-f915409beb91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787876057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2787876057
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.246032137
Short name T381
Test name
Test status
Simulation time 1709538590 ps
CPU time 23.22 seconds
Started Jun 26 06:26:46 PM PDT 24
Finished Jun 26 06:27:10 PM PDT 24
Peak memory 213404 kb
Host smart-a22adcbe-ab9d-4040-b049-8781468d5fde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246032137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.246032137
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2141006917
Short name T108
Test name
Test status
Simulation time 6361819743 ps
CPU time 67.51 seconds
Started Jun 26 06:26:19 PM PDT 24
Finished Jun 26 06:27:28 PM PDT 24
Peak memory 213364 kb
Host smart-d325ae17-b39b-4650-91c1-7cc195207994
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141006917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2141006917
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3481023434
Short name T103
Test name
Test status
Simulation time 5723690815 ps
CPU time 57.18 seconds
Started Jun 26 06:26:19 PM PDT 24
Finished Jun 26 06:27:18 PM PDT 24
Peak memory 213408 kb
Host smart-f0645a15-a854-46ce-8f13-f894ee5dde10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481023434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3481023434
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.888926103
Short name T119
Test name
Test status
Simulation time 491861299 ps
CPU time 2.59 seconds
Started Jun 26 06:26:21 PM PDT 24
Finished Jun 26 06:26:26 PM PDT 24
Peak memory 213432 kb
Host smart-154bd634-db6c-4a81-b727-06137459b1b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888926103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.888926103
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2600857084
Short name T340
Test name
Test status
Simulation time 1860838004 ps
CPU time 4.43 seconds
Started Jun 26 06:26:16 PM PDT 24
Finished Jun 26 06:26:22 PM PDT 24
Peak memory 219984 kb
Host smart-2b148551-680f-418f-813b-ca79253e84ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600857084 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2600857084
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3406793962
Short name T117
Test name
Test status
Simulation time 101622513 ps
CPU time 2.27 seconds
Started Jun 26 06:26:16 PM PDT 24
Finished Jun 26 06:26:20 PM PDT 24
Peak memory 213324 kb
Host smart-9a3e710a-a022-4cd4-937a-a17e21473a37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406793962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3406793962
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.871914381
Short name T397
Test name
Test status
Simulation time 75400456781 ps
CPU time 185.25 seconds
Started Jun 26 06:26:20 PM PDT 24
Finished Jun 26 06:29:26 PM PDT 24
Peak memory 205096 kb
Host smart-828006f7-1d6c-407f-9ad0-0ac257e43821
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871914381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.871914381
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3594001979
Short name T302
Test name
Test status
Simulation time 2458132890 ps
CPU time 3.23 seconds
Started Jun 26 06:26:17 PM PDT 24
Finished Jun 26 06:26:21 PM PDT 24
Peak memory 205004 kb
Host smart-16566bfd-21a2-4a48-98c9-c1a57b0e381a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594001979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.3594001979
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1822350044
Short name T100
Test name
Test status
Simulation time 8788126924 ps
CPU time 5 seconds
Started Jun 26 06:26:18 PM PDT 24
Finished Jun 26 06:26:24 PM PDT 24
Peak memory 205136 kb
Host smart-be78dc3e-f848-47e5-a315-530bccf4f835
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822350044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1822350044
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.99293490
Short name T399
Test name
Test status
Simulation time 5054415489 ps
CPU time 14.04 seconds
Started Jun 26 06:26:15 PM PDT 24
Finished Jun 26 06:26:30 PM PDT 24
Peak memory 205048 kb
Host smart-ba7d9d71-9bce-449f-bf22-e821c051e958
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99293490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.99293490
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3332240167
Short name T374
Test name
Test status
Simulation time 1078425196 ps
CPU time 2.21 seconds
Started Jun 26 06:26:21 PM PDT 24
Finished Jun 26 06:26:26 PM PDT 24
Peak memory 204764 kb
Host smart-651cc478-945b-427e-b1c8-5f91e8239d07
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332240167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3332240167
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1017666370
Short name T294
Test name
Test status
Simulation time 6108610992 ps
CPU time 9.31 seconds
Started Jun 26 06:26:15 PM PDT 24
Finished Jun 26 06:26:25 PM PDT 24
Peak memory 205036 kb
Host smart-51cf3e72-9ad0-47c6-80e2-c8cb414e93d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017666370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1017666370
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2680163666
Short name T425
Test name
Test status
Simulation time 425517163 ps
CPU time 1.28 seconds
Started Jun 26 06:26:20 PM PDT 24
Finished Jun 26 06:26:23 PM PDT 24
Peak memory 204484 kb
Host smart-b9a280fd-b825-4b90-860f-f3ac7b7b450b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680163666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2680163666
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2030378024
Short name T60
Test name
Test status
Simulation time 635224916 ps
CPU time 1.73 seconds
Started Jun 26 06:26:19 PM PDT 24
Finished Jun 26 06:26:22 PM PDT 24
Peak memory 204788 kb
Host smart-5bb46610-37cc-4af3-969b-8c083a5262a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030378024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
030378024
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3049201980
Short name T369
Test name
Test status
Simulation time 124959221 ps
CPU time 0.83 seconds
Started Jun 26 06:26:15 PM PDT 24
Finished Jun 26 06:26:17 PM PDT 24
Peak memory 204808 kb
Host smart-0f4f27aa-7c24-4e4c-b4ce-c2d8017e26e4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049201980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3049201980
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2737552610
Short name T290
Test name
Test status
Simulation time 93389704 ps
CPU time 0.79 seconds
Started Jun 26 06:26:17 PM PDT 24
Finished Jun 26 06:26:19 PM PDT 24
Peak memory 204728 kb
Host smart-956a68a8-4c4c-47a5-9213-b2a3cf4ac759
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737552610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2737552610
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.833817982
Short name T394
Test name
Test status
Simulation time 91767083 ps
CPU time 3.68 seconds
Started Jun 26 06:26:19 PM PDT 24
Finished Jun 26 06:26:24 PM PDT 24
Peak memory 205176 kb
Host smart-55421da0-f316-4861-b51f-13acd1e2727a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833817982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.833817982
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3690800180
Short name T133
Test name
Test status
Simulation time 1465360631 ps
CPU time 3.89 seconds
Started Jun 26 06:26:16 PM PDT 24
Finished Jun 26 06:26:22 PM PDT 24
Peak memory 213388 kb
Host smart-c10c8ad6-6f21-4a86-98f8-0a8985336a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690800180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3690800180
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2723009784
Short name T118
Test name
Test status
Simulation time 10626291697 ps
CPU time 77.09 seconds
Started Jun 26 06:26:15 PM PDT 24
Finished Jun 26 06:27:33 PM PDT 24
Peak memory 213408 kb
Host smart-5176cf74-67dc-4603-bced-f7998ad7b06e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723009784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2723009784
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1241100553
Short name T370
Test name
Test status
Simulation time 5136597386 ps
CPU time 34.44 seconds
Started Jun 26 06:26:24 PM PDT 24
Finished Jun 26 06:27:00 PM PDT 24
Peak memory 213620 kb
Host smart-7e765315-9930-4152-aadf-ec0f0d761b26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241100553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1241100553
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1477614988
Short name T111
Test name
Test status
Simulation time 202812202 ps
CPU time 2.03 seconds
Started Jun 26 06:26:22 PM PDT 24
Finished Jun 26 06:26:26 PM PDT 24
Peak memory 213328 kb
Host smart-fa49698d-b735-497d-906d-68344bb0b597
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477614988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1477614988
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2650236426
Short name T320
Test name
Test status
Simulation time 1920597532 ps
CPU time 7.01 seconds
Started Jun 26 06:26:23 PM PDT 24
Finished Jun 26 06:26:32 PM PDT 24
Peak memory 221576 kb
Host smart-08061315-093b-442c-b79c-1d59cdd1f3b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650236426 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2650236426
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.361801859
Short name T116
Test name
Test status
Simulation time 116995444 ps
CPU time 2.49 seconds
Started Jun 26 06:26:23 PM PDT 24
Finished Jun 26 06:26:29 PM PDT 24
Peak memory 213292 kb
Host smart-f2442d96-3588-472c-8d46-b3fce32aa3c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361801859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.361801859
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.914484788
Short name T418
Test name
Test status
Simulation time 64304884219 ps
CPU time 91.87 seconds
Started Jun 26 06:26:16 PM PDT 24
Finished Jun 26 06:27:49 PM PDT 24
Peak memory 205032 kb
Host smart-b6807669-116a-412f-9928-ff673be25df0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914484788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.914484788
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3048183112
Short name T378
Test name
Test status
Simulation time 5923750157 ps
CPU time 15.96 seconds
Started Jun 26 06:26:17 PM PDT 24
Finished Jun 26 06:26:34 PM PDT 24
Peak memory 205028 kb
Host smart-608880b6-84fb-44ff-9b81-254b128da35d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048183112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.3048183112
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4032462199
Short name T102
Test name
Test status
Simulation time 9942248623 ps
CPU time 23.85 seconds
Started Jun 26 06:26:17 PM PDT 24
Finished Jun 26 06:26:42 PM PDT 24
Peak memory 205120 kb
Host smart-281cca24-29f6-456e-8564-6dde55a25668
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032462199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.4032462199
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3625670065
Short name T350
Test name
Test status
Simulation time 6819968987 ps
CPU time 18.58 seconds
Started Jun 26 06:26:18 PM PDT 24
Finished Jun 26 06:26:38 PM PDT 24
Peak memory 205032 kb
Host smart-67e62e12-ca65-44d6-9094-deaba64005c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625670065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
625670065
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3488816937
Short name T296
Test name
Test status
Simulation time 312120503 ps
CPU time 1.58 seconds
Started Jun 26 06:26:16 PM PDT 24
Finished Jun 26 06:26:18 PM PDT 24
Peak memory 204780 kb
Host smart-944d6434-20ef-4c1a-b718-16eac74698a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488816937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3488816937
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.64420457
Short name T329
Test name
Test status
Simulation time 49324688717 ps
CPU time 124.59 seconds
Started Jun 26 06:26:20 PM PDT 24
Finished Jun 26 06:28:26 PM PDT 24
Peak memory 205276 kb
Host smart-e3bd13fc-17ef-4701-9a70-942ba36547f9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64420457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_
bit_bash.64420457
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2867064939
Short name T421
Test name
Test status
Simulation time 546795813 ps
CPU time 1.01 seconds
Started Jun 26 06:26:20 PM PDT 24
Finished Jun 26 06:26:22 PM PDT 24
Peak memory 204468 kb
Host smart-440b9c94-c35b-4d73-835d-6999cd888e15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867064939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2867064939
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.256295851
Short name T372
Test name
Test status
Simulation time 996725131 ps
CPU time 2.91 seconds
Started Jun 26 06:26:17 PM PDT 24
Finished Jun 26 06:26:21 PM PDT 24
Peak memory 204756 kb
Host smart-c1818ab7-db7b-428a-b9f5-4b259a602d66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256295851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.256295851
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2629502699
Short name T291
Test name
Test status
Simulation time 61697056 ps
CPU time 0.71 seconds
Started Jun 26 06:26:23 PM PDT 24
Finished Jun 26 06:26:26 PM PDT 24
Peak memory 205056 kb
Host smart-ac2393ed-b62e-481a-abe8-e8ace17a5581
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629502699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2629502699
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.971941881
Short name T339
Test name
Test status
Simulation time 127616350 ps
CPU time 0.99 seconds
Started Jun 26 06:26:21 PM PDT 24
Finished Jun 26 06:26:24 PM PDT 24
Peak memory 204768 kb
Host smart-837d1203-92aa-4b88-89fb-dc9e8769e795
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971941881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.971941881
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3835762694
Short name T107
Test name
Test status
Simulation time 440838763 ps
CPU time 6.61 seconds
Started Jun 26 06:26:22 PM PDT 24
Finished Jun 26 06:26:31 PM PDT 24
Peak memory 205180 kb
Host smart-a04fc4a4-e818-41aa-9443-bdc89166eada
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835762694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3835762694
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.248559630
Short name T333
Test name
Test status
Simulation time 171388268 ps
CPU time 4 seconds
Started Jun 26 06:26:15 PM PDT 24
Finished Jun 26 06:26:20 PM PDT 24
Peak memory 213384 kb
Host smart-687cdfd2-ad70-4d36-a8ef-d6f61c9642a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248559630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.248559630
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2460630410
Short name T406
Test name
Test status
Simulation time 6325914909 ps
CPU time 32.62 seconds
Started Jun 26 06:26:17 PM PDT 24
Finished Jun 26 06:26:50 PM PDT 24
Peak memory 213484 kb
Host smart-3e8d3e14-4330-40e6-9aea-e950e0885529
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460630410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2460630410
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1396510164
Short name T67
Test name
Test status
Simulation time 3439706010 ps
CPU time 28.31 seconds
Started Jun 26 06:26:22 PM PDT 24
Finished Jun 26 06:26:53 PM PDT 24
Peak memory 213324 kb
Host smart-0bd6465b-2ad1-4e61-9f7f-eeeabaaa3d6e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396510164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1396510164
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1534511804
Short name T367
Test name
Test status
Simulation time 23267852325 ps
CPU time 75.09 seconds
Started Jun 26 06:26:26 PM PDT 24
Finished Jun 26 06:27:43 PM PDT 24
Peak memory 205204 kb
Host smart-57b4d4f8-3c71-4b38-bbb6-9aa4b37e1f96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534511804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1534511804
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2794323086
Short name T359
Test name
Test status
Simulation time 436083987 ps
CPU time 3.35 seconds
Started Jun 26 06:26:22 PM PDT 24
Finished Jun 26 06:26:28 PM PDT 24
Peak memory 213264 kb
Host smart-43e3c57c-07c9-4a12-a84e-dadec2e2a5aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794323086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2794323086
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2823159462
Short name T313
Test name
Test status
Simulation time 1937650084 ps
CPU time 5.29 seconds
Started Jun 26 06:26:23 PM PDT 24
Finished Jun 26 06:26:30 PM PDT 24
Peak memory 213336 kb
Host smart-7a706f4f-6686-4642-8351-fbcbf639b7d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823159462 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2823159462
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3106769929
Short name T292
Test name
Test status
Simulation time 46953737986 ps
CPU time 92.35 seconds
Started Jun 26 06:26:24 PM PDT 24
Finished Jun 26 06:27:59 PM PDT 24
Peak memory 205248 kb
Host smart-a95a4833-9ed5-497f-b861-fdf3d970bf03
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106769929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3106769929
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1930949218
Short name T401
Test name
Test status
Simulation time 4393980975 ps
CPU time 11.42 seconds
Started Jun 26 06:26:23 PM PDT 24
Finished Jun 26 06:26:36 PM PDT 24
Peak memory 205060 kb
Host smart-fdea1130-f9d5-43af-9e32-4e41dfc20b59
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930949218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.1930949218
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1100493217
Short name T305
Test name
Test status
Simulation time 2669536639 ps
CPU time 2.91 seconds
Started Jun 26 06:26:22 PM PDT 24
Finished Jun 26 06:26:27 PM PDT 24
Peak memory 205084 kb
Host smart-e8fe4d95-d316-4408-bbca-8af8fd8a34d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100493217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1100493217
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3109674243
Short name T414
Test name
Test status
Simulation time 898017778 ps
CPU time 3.4 seconds
Started Jun 26 06:26:26 PM PDT 24
Finished Jun 26 06:26:31 PM PDT 24
Peak memory 204992 kb
Host smart-fcfb6399-833f-4482-908f-7a5f6173c391
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109674243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
109674243
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1147883378
Short name T407
Test name
Test status
Simulation time 2108093764 ps
CPU time 2.38 seconds
Started Jun 26 06:26:25 PM PDT 24
Finished Jun 26 06:26:30 PM PDT 24
Peak memory 204780 kb
Host smart-aea1fb3c-fc05-4a66-965d-ee7df7c266a0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147883378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1147883378
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2219361107
Short name T301
Test name
Test status
Simulation time 25456981816 ps
CPU time 68.02 seconds
Started Jun 26 06:26:29 PM PDT 24
Finished Jun 26 06:27:38 PM PDT 24
Peak memory 205100 kb
Host smart-7513259e-b0cd-4d0d-8cc7-ca7d98f3fa95
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219361107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2219361107
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.559321065
Short name T338
Test name
Test status
Simulation time 878715891 ps
CPU time 2.94 seconds
Started Jun 26 06:26:24 PM PDT 24
Finished Jun 26 06:26:29 PM PDT 24
Peak memory 204704 kb
Host smart-ba83b1e7-746a-4b17-a842-c6c1a3a1b63c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559321065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.559321065
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4161116305
Short name T328
Test name
Test status
Simulation time 853084086 ps
CPU time 0.85 seconds
Started Jun 26 06:26:24 PM PDT 24
Finished Jun 26 06:26:28 PM PDT 24
Peak memory 204760 kb
Host smart-7bb6c41d-f9a7-4952-802f-4a2fc7048dbb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161116305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.4
161116305
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4062141977
Short name T347
Test name
Test status
Simulation time 45860869 ps
CPU time 0.79 seconds
Started Jun 26 06:26:22 PM PDT 24
Finished Jun 26 06:26:25 PM PDT 24
Peak memory 204832 kb
Host smart-fbff130a-9672-4b68-b4f5-02ddca1bc5d2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062141977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.4062141977
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.923592217
Short name T304
Test name
Test status
Simulation time 104182259 ps
CPU time 0.69 seconds
Started Jun 26 06:26:29 PM PDT 24
Finished Jun 26 06:26:30 PM PDT 24
Peak memory 204768 kb
Host smart-41d60b41-aeb0-447d-96d4-27f103295133
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923592217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.923592217
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.140325116
Short name T110
Test name
Test status
Simulation time 345062771 ps
CPU time 3.76 seconds
Started Jun 26 06:26:23 PM PDT 24
Finished Jun 26 06:26:30 PM PDT 24
Peak memory 205240 kb
Host smart-5a51613e-996c-47c1-880c-933118c8150b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140325116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.140325116
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3492581960
Short name T412
Test name
Test status
Simulation time 157757313 ps
CPU time 2.5 seconds
Started Jun 26 06:26:26 PM PDT 24
Finished Jun 26 06:26:30 PM PDT 24
Peak memory 213376 kb
Host smart-98f485eb-09ea-4749-a733-a66d0a688cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492581960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3492581960
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2707650930
Short name T64
Test name
Test status
Simulation time 803861087 ps
CPU time 3.76 seconds
Started Jun 26 06:26:26 PM PDT 24
Finished Jun 26 06:26:32 PM PDT 24
Peak memory 219028 kb
Host smart-506138cd-279e-486f-930e-47c2fab90b66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707650930 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2707650930
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.720198962
Short name T335
Test name
Test status
Simulation time 754694877 ps
CPU time 1.51 seconds
Started Jun 26 06:26:27 PM PDT 24
Finished Jun 26 06:26:30 PM PDT 24
Peak memory 213264 kb
Host smart-0f600782-dad8-4a0a-91e8-eccedfead4de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720198962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.720198962
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1439932062
Short name T386
Test name
Test status
Simulation time 13754298559 ps
CPU time 17.17 seconds
Started Jun 26 06:26:25 PM PDT 24
Finished Jun 26 06:26:45 PM PDT 24
Peak memory 204996 kb
Host smart-41bf54c9-d62c-41fe-86f8-100ad2e7ccdf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439932062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.1439932062
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3855060822
Short name T357
Test name
Test status
Simulation time 7430054587 ps
CPU time 9.95 seconds
Started Jun 26 06:26:58 PM PDT 24
Finished Jun 26 06:27:09 PM PDT 24
Peak memory 205036 kb
Host smart-e5421714-3a3b-4038-b564-777dc19f0563
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855060822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
855060822
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.283520135
Short name T419
Test name
Test status
Simulation time 810996906 ps
CPU time 1.78 seconds
Started Jun 26 06:26:24 PM PDT 24
Finished Jun 26 06:26:28 PM PDT 24
Peak memory 204764 kb
Host smart-a4498f93-cb64-4165-92d0-23b7f77aadd5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283520135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.283520135
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2875811004
Short name T104
Test name
Test status
Simulation time 374667044 ps
CPU time 6.52 seconds
Started Jun 26 06:26:24 PM PDT 24
Finished Jun 26 06:26:33 PM PDT 24
Peak memory 205184 kb
Host smart-b7b6382b-75bc-44ac-b98e-bfe03dfd7938
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875811004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2875811004
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1406196057
Short name T351
Test name
Test status
Simulation time 208176326 ps
CPU time 2.93 seconds
Started Jun 26 06:26:24 PM PDT 24
Finished Jun 26 06:26:29 PM PDT 24
Peak memory 213364 kb
Host smart-8ab5f783-d638-4add-8cda-e9de1404168b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406196057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1406196057
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3911837944
Short name T141
Test name
Test status
Simulation time 1395657934 ps
CPU time 18.68 seconds
Started Jun 26 06:26:24 PM PDT 24
Finished Jun 26 06:26:46 PM PDT 24
Peak memory 213408 kb
Host smart-607da0f6-4516-49d0-85c5-7df0ebf35bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911837944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3911837944
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1001548642
Short name T396
Test name
Test status
Simulation time 486251677 ps
CPU time 4.07 seconds
Started Jun 26 06:26:26 PM PDT 24
Finished Jun 26 06:26:32 PM PDT 24
Peak memory 213460 kb
Host smart-77123e81-def6-480a-853c-ca197232e9db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001548642 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1001548642
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.473722225
Short name T98
Test name
Test status
Simulation time 508638687 ps
CPU time 2.32 seconds
Started Jun 26 06:26:22 PM PDT 24
Finished Jun 26 06:26:26 PM PDT 24
Peak memory 213280 kb
Host smart-7e194c35-ad12-43e5-81b4-6ab8795f0767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473722225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.473722225
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.978382938
Short name T289
Test name
Test status
Simulation time 134563224 ps
CPU time 0.97 seconds
Started Jun 26 06:26:22 PM PDT 24
Finished Jun 26 06:26:25 PM PDT 24
Peak memory 204764 kb
Host smart-71b1a8e4-1f8d-435e-b67e-dea50bc754b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978382938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
v_dm_jtag_dmi_csr_bit_bash.978382938
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2441103831
Short name T293
Test name
Test status
Simulation time 4659046662 ps
CPU time 9.87 seconds
Started Jun 26 06:26:24 PM PDT 24
Finished Jun 26 06:26:37 PM PDT 24
Peak memory 205056 kb
Host smart-568e8d14-4149-4712-8b2b-445b0f1515ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441103831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
441103831
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3629763708
Short name T361
Test name
Test status
Simulation time 1222261197 ps
CPU time 1.09 seconds
Started Jun 26 06:26:23 PM PDT 24
Finished Jun 26 06:26:27 PM PDT 24
Peak memory 204752 kb
Host smart-6e039719-80d6-4b92-95c5-f202136ae4b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629763708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
629763708
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1810330645
Short name T90
Test name
Test status
Simulation time 3136287430 ps
CPU time 7.84 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:40 PM PDT 24
Peak memory 205280 kb
Host smart-5eb17ecb-eabf-4296-9e77-4cb398967f34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810330645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1810330645
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2820659203
Short name T125
Test name
Test status
Simulation time 207203609 ps
CPU time 3.82 seconds
Started Jun 26 06:26:29 PM PDT 24
Finished Jun 26 06:26:34 PM PDT 24
Peak memory 213360 kb
Host smart-18b519f2-41e3-402c-87a6-14346ff364e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820659203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2820659203
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1894771612
Short name T65
Test name
Test status
Simulation time 3561186294 ps
CPU time 13.73 seconds
Started Jun 26 06:26:26 PM PDT 24
Finished Jun 26 06:26:41 PM PDT 24
Peak memory 221656 kb
Host smart-ebc4cda7-77c3-413f-a1fb-73966bb685f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894771612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1894771612
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2929978534
Short name T356
Test name
Test status
Simulation time 4781692305 ps
CPU time 7.6 seconds
Started Jun 26 06:26:29 PM PDT 24
Finished Jun 26 06:26:38 PM PDT 24
Peak memory 221632 kb
Host smart-86547eac-efd3-4c8a-8dcb-685a83c5a955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929978534 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2929978534
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.134503761
Short name T389
Test name
Test status
Simulation time 218079931 ps
CPU time 2.65 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:36 PM PDT 24
Peak memory 213236 kb
Host smart-a4fccd41-349d-4621-b2c0-e1a6fa067d3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134503761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.134503761
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1426242114
Short name T404
Test name
Test status
Simulation time 9672653271 ps
CPU time 12.67 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:46 PM PDT 24
Peak memory 205268 kb
Host smart-742728d8-e6ab-4c48-af6e-66f5bab1aa2e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426242114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.1426242114
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2266924500
Short name T385
Test name
Test status
Simulation time 1740605587 ps
CPU time 3.14 seconds
Started Jun 26 06:26:23 PM PDT 24
Finished Jun 26 06:26:28 PM PDT 24
Peak memory 204956 kb
Host smart-e12c5e14-343f-4bed-b02d-2b29402464d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266924500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
266924500
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2438121681
Short name T61
Test name
Test status
Simulation time 351449056 ps
CPU time 0.84 seconds
Started Jun 26 06:26:27 PM PDT 24
Finished Jun 26 06:26:29 PM PDT 24
Peak memory 204760 kb
Host smart-0e9ff31c-3ab2-4858-ab4d-55d7f61fdfca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438121681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
438121681
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3853732871
Short name T388
Test name
Test status
Simulation time 6538756533 ps
CPU time 9.56 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:42 PM PDT 24
Peak memory 205304 kb
Host smart-b83d3aa1-aa0f-44a4-a223-bc10c8543cfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853732871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3853732871
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2494501795
Short name T364
Test name
Test status
Simulation time 162486095 ps
CPU time 4.05 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:37 PM PDT 24
Peak memory 213388 kb
Host smart-f6fb6d18-5f9d-4ba3-b18f-590f84147340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494501795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2494501795
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1562278237
Short name T403
Test name
Test status
Simulation time 3943176973 ps
CPU time 9.77 seconds
Started Jun 26 06:26:33 PM PDT 24
Finished Jun 26 06:26:44 PM PDT 24
Peak memory 213444 kb
Host smart-ac40b9c2-4076-4d46-a0a7-6765d573909f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562278237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1562278237
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3199828503
Short name T129
Test name
Test status
Simulation time 2329120345 ps
CPU time 7.17 seconds
Started Jun 26 06:26:29 PM PDT 24
Finished Jun 26 06:26:38 PM PDT 24
Peak memory 221568 kb
Host smart-c361d73c-2919-425a-b481-36b5ab6a7e61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199828503 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3199828503
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3760466058
Short name T123
Test name
Test status
Simulation time 45621407 ps
CPU time 1.55 seconds
Started Jun 26 06:26:30 PM PDT 24
Finished Jun 26 06:26:33 PM PDT 24
Peak memory 213312 kb
Host smart-9a909f3a-5c94-4b63-80c0-55d44bc24d1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760466058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3760466058
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1691416563
Short name T382
Test name
Test status
Simulation time 50364080632 ps
CPU time 36.13 seconds
Started Jun 26 06:26:30 PM PDT 24
Finished Jun 26 06:27:08 PM PDT 24
Peak memory 204992 kb
Host smart-b0c5e32e-de78-4b7a-bdaf-ca97018096d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691416563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1691416563
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.517848105
Short name T373
Test name
Test status
Simulation time 4780770925 ps
CPU time 6.99 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:39 PM PDT 24
Peak memory 205020 kb
Host smart-807dfad4-e4c3-4b11-9b91-4ba053719d21
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517848105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.517848105
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3509158949
Short name T332
Test name
Test status
Simulation time 480207580 ps
CPU time 1.23 seconds
Started Jun 26 06:26:29 PM PDT 24
Finished Jun 26 06:26:31 PM PDT 24
Peak memory 204788 kb
Host smart-a2240589-ff81-4fd2-9e56-cbf3a8c74ccb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509158949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
509158949
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.800765987
Short name T405
Test name
Test status
Simulation time 168442729 ps
CPU time 6.83 seconds
Started Jun 26 06:26:32 PM PDT 24
Finished Jun 26 06:26:41 PM PDT 24
Peak memory 205152 kb
Host smart-7d9c8fa1-6b60-4c85-99dc-bae7a1974b46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800765987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.800765987
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.446617226
Short name T413
Test name
Test status
Simulation time 151147020 ps
CPU time 3.39 seconds
Started Jun 26 06:26:34 PM PDT 24
Finished Jun 26 06:26:38 PM PDT 24
Peak memory 213404 kb
Host smart-c7dbaad3-8a29-47e8-a98f-3b57a8403198
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446617226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.446617226
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3292696461
Short name T86
Test name
Test status
Simulation time 346434339 ps
CPU time 2.32 seconds
Started Jun 26 06:26:34 PM PDT 24
Finished Jun 26 06:26:37 PM PDT 24
Peak memory 221604 kb
Host smart-bd6d568e-95fc-4499-8bcf-3f8d473a1fc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292696461 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3292696461
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1704172762
Short name T330
Test name
Test status
Simulation time 193542226 ps
CPU time 1.61 seconds
Started Jun 26 06:26:32 PM PDT 24
Finished Jun 26 06:26:35 PM PDT 24
Peak memory 213340 kb
Host smart-f55f891f-7b1c-4a06-b7b9-882e2231df75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704172762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1704172762
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.792170964
Short name T391
Test name
Test status
Simulation time 11965826700 ps
CPU time 9.02 seconds
Started Jun 26 06:26:30 PM PDT 24
Finished Jun 26 06:26:40 PM PDT 24
Peak memory 205068 kb
Host smart-1c2b5e1e-61a2-40c0-9f84-aafbec2a99ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792170964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
v_dm_jtag_dmi_csr_bit_bash.792170964
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.153205673
Short name T410
Test name
Test status
Simulation time 1550450264 ps
CPU time 1.92 seconds
Started Jun 26 06:26:32 PM PDT 24
Finished Jun 26 06:26:36 PM PDT 24
Peak memory 204904 kb
Host smart-4accb3ff-3394-4b78-b0c1-7166778084e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153205673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.153205673
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3755288178
Short name T337
Test name
Test status
Simulation time 370227756 ps
CPU time 1.66 seconds
Started Jun 26 06:26:30 PM PDT 24
Finished Jun 26 06:26:34 PM PDT 24
Peak memory 204764 kb
Host smart-23487cba-2b6e-4b3e-b4f9-75c605d075bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755288178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
755288178
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.57051538
Short name T120
Test name
Test status
Simulation time 2200175195 ps
CPU time 8.07 seconds
Started Jun 26 06:26:32 PM PDT 24
Finished Jun 26 06:26:42 PM PDT 24
Peak memory 205248 kb
Host smart-5b1cb855-d548-4f11-9aeb-8aa6bb651deb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57051538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_cs
r_outstanding.57051538
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2021164888
Short name T309
Test name
Test status
Simulation time 976371765 ps
CPU time 5.95 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:39 PM PDT 24
Peak memory 213216 kb
Host smart-c56f99bb-9219-491f-b170-4bbcd514e4dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021164888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2021164888
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2970193784
Short name T344
Test name
Test status
Simulation time 4508956010 ps
CPU time 12.71 seconds
Started Jun 26 06:26:31 PM PDT 24
Finished Jun 26 06:26:45 PM PDT 24
Peak memory 213500 kb
Host smart-992a8f69-cc85-4b2b-8ff4-0cb64d175d18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970193784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2970193784
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3905985774
Short name T163
Test name
Test status
Simulation time 129265728 ps
CPU time 0.82 seconds
Started Jun 26 06:58:17 PM PDT 24
Finished Jun 26 06:58:21 PM PDT 24
Peak memory 205032 kb
Host smart-e3479da6-dd72-4237-a26f-f69f0ad013d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905985774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3905985774
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2129388762
Short name T285
Test name
Test status
Simulation time 53573378147 ps
CPU time 150.83 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 07:00:53 PM PDT 24
Peak memory 213540 kb
Host smart-47a1d41e-26a0-495d-a287-3e2b03805fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129388762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2129388762
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2496383987
Short name T219
Test name
Test status
Simulation time 3524606654 ps
CPU time 4.19 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:29 PM PDT 24
Peak memory 205376 kb
Host smart-8adee0ff-32e2-4a54-bbc8-92c5e9769095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496383987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2496383987
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1657280193
Short name T12
Test name
Test status
Simulation time 1031685409 ps
CPU time 2.16 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:25 PM PDT 24
Peak memory 205016 kb
Host smart-739b7159-c94f-4372-ba32-d96c62c9236e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657280193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1657280193
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1682001321
Short name T158
Test name
Test status
Simulation time 1043219643 ps
CPU time 3.11 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 06:58:26 PM PDT 24
Peak memory 205008 kb
Host smart-d0381a98-6c23-4dc2-8476-a633e817b522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682001321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1682001321
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2499273108
Short name T288
Test name
Test status
Simulation time 294550392 ps
CPU time 1.03 seconds
Started Jun 26 06:58:17 PM PDT 24
Finished Jun 26 06:58:22 PM PDT 24
Peak memory 204940 kb
Host smart-7e338aa8-4d92-497c-85c5-a2bc43f59a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499273108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2499273108
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.4158881145
Short name T39
Test name
Test status
Simulation time 19462029 ps
CPU time 0.82 seconds
Started Jun 26 06:58:16 PM PDT 24
Finished Jun 26 06:58:19 PM PDT 24
Peak memory 223040 kb
Host smart-7007fe28-277b-4a8f-8f46-bb2b53cd5ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158881145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.4158881145
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1937563273
Short name T198
Test name
Test status
Simulation time 3100409032 ps
CPU time 9.47 seconds
Started Jun 26 06:58:17 PM PDT 24
Finished Jun 26 06:58:30 PM PDT 24
Peak memory 205424 kb
Host smart-671585af-f749-4879-82bc-2fd627d7d81f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937563273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1937563273
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3271820543
Short name T144
Test name
Test status
Simulation time 1720875778 ps
CPU time 2.68 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:26 PM PDT 24
Peak memory 204932 kb
Host smart-a13899cc-ca72-4c1a-9d87-50237f5aebab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271820543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3271820543
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3483924671
Short name T255
Test name
Test status
Simulation time 189713780 ps
CPU time 0.85 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:24 PM PDT 24
Peak memory 204840 kb
Host smart-e77f4196-0320-4970-ae39-cc57a8a98768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483924671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3483924671
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1785242972
Short name T1
Test name
Test status
Simulation time 1130689797 ps
CPU time 3.75 seconds
Started Jun 26 06:58:15 PM PDT 24
Finished Jun 26 06:58:21 PM PDT 24
Peak memory 204808 kb
Host smart-6761a1c1-5931-42a8-8e52-9bcfc8e8c45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785242972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1785242972
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.102527470
Short name T42
Test name
Test status
Simulation time 383046795 ps
CPU time 1.87 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:25 PM PDT 24
Peak memory 204796 kb
Host smart-1db1b545-554d-4b96-8444-0a85af0df994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102527470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.102527470
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1148084102
Short name T224
Test name
Test status
Simulation time 2311608041 ps
CPU time 6.11 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:30 PM PDT 24
Peak memory 204976 kb
Host smart-15eede8e-1a7b-4517-a1ff-db9b0ef26387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148084102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1148084102
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.332808875
Short name T189
Test name
Test status
Simulation time 123847598 ps
CPU time 0.69 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:24 PM PDT 24
Peak memory 204800 kb
Host smart-812d8b66-ffb1-411b-ada4-09ad08146cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332808875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.332808875
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.616549778
Short name T156
Test name
Test status
Simulation time 1286153050 ps
CPU time 1.46 seconds
Started Jun 26 06:58:17 PM PDT 24
Finished Jun 26 06:58:21 PM PDT 24
Peak memory 204944 kb
Host smart-6bad9668-fc91-4eee-807a-627b56a34566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616549778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.616549778
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.713785845
Short name T159
Test name
Test status
Simulation time 4018680709 ps
CPU time 11.62 seconds
Started Jun 26 06:58:17 PM PDT 24
Finished Jun 26 06:58:33 PM PDT 24
Peak memory 205008 kb
Host smart-d0f3029c-42cb-49fc-b182-ec1c4a1a1629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713785845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.713785845
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1882875709
Short name T89
Test name
Test status
Simulation time 477714690 ps
CPU time 1 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 06:58:23 PM PDT 24
Peak memory 204956 kb
Host smart-df61f1ed-48e7-40d3-ae6d-6987c9100842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882875709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1882875709
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2514642170
Short name T191
Test name
Test status
Simulation time 595668225 ps
CPU time 1.55 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 06:58:24 PM PDT 24
Peak memory 204804 kb
Host smart-569c9430-b562-4f30-977e-e0b925bdfdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514642170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2514642170
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2254889800
Short name T234
Test name
Test status
Simulation time 1333783654 ps
CPU time 4.68 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:28 PM PDT 24
Peak memory 205364 kb
Host smart-d4275cfb-bcd7-4dfc-ba5a-250a18113e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254889800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2254889800
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.599230818
Short name T33
Test name
Test status
Simulation time 657709712 ps
CPU time 1.43 seconds
Started Jun 26 06:58:16 PM PDT 24
Finished Jun 26 06:58:20 PM PDT 24
Peak memory 204824 kb
Host smart-bdd85e4e-b2b9-4893-a80d-07a5cb82c879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599230818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.599230818
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.2398142220
Short name T53
Test name
Test status
Simulation time 144490806 ps
CPU time 0.9 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 06:58:23 PM PDT 24
Peak memory 204932 kb
Host smart-c42cc312-dadb-4142-811b-2c70aa4119c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398142220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2398142220
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.183231646
Short name T173
Test name
Test status
Simulation time 170696579 ps
CPU time 0.88 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:25 PM PDT 24
Peak memory 205020 kb
Host smart-fd703b04-7a53-486c-9355-f309aeaa648d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183231646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.183231646
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1140559138
Short name T274
Test name
Test status
Simulation time 116412777841 ps
CPU time 106.97 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 07:00:10 PM PDT 24
Peak memory 219100 kb
Host smart-86c3cf79-2f68-4984-b0c9-ff8cb64074f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140559138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1140559138
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1564952774
Short name T280
Test name
Test status
Simulation time 7824827470 ps
CPU time 17.35 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:40 PM PDT 24
Peak memory 205384 kb
Host smart-73305b5d-f84d-49bc-90b7-21f6b483cfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564952774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1564952774
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2587836045
Short name T13
Test name
Test status
Simulation time 1322429553 ps
CPU time 4.36 seconds
Started Jun 26 06:58:16 PM PDT 24
Finished Jun 26 06:58:23 PM PDT 24
Peak memory 204936 kb
Host smart-1851e4be-cf2c-4169-9eec-b9c5346a62d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587836045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2587836045
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1082290737
Short name T54
Test name
Test status
Simulation time 538377685 ps
CPU time 2.04 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 06:58:24 PM PDT 24
Peak memory 204920 kb
Host smart-fe16da38-b792-4703-8434-83173cd71d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082290737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1082290737
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1867205454
Short name T48
Test name
Test status
Simulation time 2413607102 ps
CPU time 4.12 seconds
Started Jun 26 06:58:15 PM PDT 24
Finished Jun 26 06:58:22 PM PDT 24
Peak memory 204860 kb
Host smart-94bbd41a-8909-4b72-8971-d374d7308a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867205454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1867205454
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2790262331
Short name T210
Test name
Test status
Simulation time 176368127 ps
CPU time 0.92 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:25 PM PDT 24
Peak memory 204892 kb
Host smart-fe87564f-8c67-470e-81e2-ac13d047647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790262331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2790262331
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3759932914
Short name T153
Test name
Test status
Simulation time 369671954 ps
CPU time 1.29 seconds
Started Jun 26 06:58:17 PM PDT 24
Finished Jun 26 06:58:22 PM PDT 24
Peak memory 204968 kb
Host smart-878cd872-3cfc-4333-86b3-447f9afca90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759932914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3759932914
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.794731002
Short name T47
Test name
Test status
Simulation time 1197100516 ps
CPU time 2.61 seconds
Started Jun 26 06:58:14 PM PDT 24
Finished Jun 26 06:58:19 PM PDT 24
Peak memory 205312 kb
Host smart-6fdd17c5-12ea-4e8c-8442-fb930a4d971d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794731002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl
_access.794731002
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3725893387
Short name T157
Test name
Test status
Simulation time 804133482 ps
CPU time 1.84 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 06:58:24 PM PDT 24
Peak memory 204956 kb
Host smart-8d801b4a-a46e-4f0e-99c1-06a08c59635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725893387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3725893387
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1421901050
Short name T250
Test name
Test status
Simulation time 80211622 ps
CPU time 0.92 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:25 PM PDT 24
Peak memory 204744 kb
Host smart-023531cd-96cf-45d8-abdf-e1a0b0c73953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421901050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1421901050
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.141290551
Short name T264
Test name
Test status
Simulation time 149035081 ps
CPU time 0.87 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:24 PM PDT 24
Peak memory 204844 kb
Host smart-e73e29c7-5f98-48c7-a205-2e52ea05170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141290551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.141290551
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.866870079
Short name T227
Test name
Test status
Simulation time 2119484423 ps
CPU time 6.28 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:29 PM PDT 24
Peak memory 204812 kb
Host smart-51f9c87e-fcb1-4759-883f-d907769128e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866870079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.866870079
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.477403553
Short name T230
Test name
Test status
Simulation time 541641988 ps
CPU time 2.29 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:26 PM PDT 24
Peak memory 204800 kb
Host smart-ab4f438f-d243-4fb7-a732-eb613688f70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477403553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.477403553
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.37523587
Short name T57
Test name
Test status
Simulation time 398334857 ps
CPU time 0.92 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:25 PM PDT 24
Peak memory 204820 kb
Host smart-dec74037-1600-4aa0-9143-6420d384075e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37523587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.37523587
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1702868698
Short name T35
Test name
Test status
Simulation time 651215205 ps
CPU time 2.31 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 06:58:24 PM PDT 24
Peak memory 204980 kb
Host smart-a3b8f820-5654-4237-926a-a670c3ad4fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702868698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1702868698
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2634565093
Short name T160
Test name
Test status
Simulation time 1863086291 ps
CPU time 3.51 seconds
Started Jun 26 06:58:15 PM PDT 24
Finished Jun 26 06:58:21 PM PDT 24
Peak memory 205200 kb
Host smart-74d0397d-bcd2-402f-9b3e-1f1245a7407b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634565093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2634565093
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.552913991
Short name T88
Test name
Test status
Simulation time 439132790 ps
CPU time 1.07 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:24 PM PDT 24
Peak memory 204944 kb
Host smart-02e5487d-eefc-4755-ac54-c7972e58be91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552913991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.552913991
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.354819348
Short name T17
Test name
Test status
Simulation time 659655012 ps
CPU time 1.17 seconds
Started Jun 26 06:58:17 PM PDT 24
Finished Jun 26 06:58:22 PM PDT 24
Peak memory 204908 kb
Host smart-5e709035-d494-4a35-bb6f-bc355a9af98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354819348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.354819348
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.367350074
Short name T55
Test name
Test status
Simulation time 327124498 ps
CPU time 0.98 seconds
Started Jun 26 06:58:19 PM PDT 24
Finished Jun 26 06:58:24 PM PDT 24
Peak memory 204920 kb
Host smart-bec2392d-709d-4c05-b7d4-4ffd96e629af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367350074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.367350074
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.231799505
Short name T50
Test name
Test status
Simulation time 62454525 ps
CPU time 0.84 seconds
Started Jun 26 06:58:21 PM PDT 24
Finished Jun 26 06:58:26 PM PDT 24
Peak memory 215712 kb
Host smart-4c1fec7b-7846-490b-a51a-6455ef82efdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231799505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.231799505
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2531948097
Short name T249
Test name
Test status
Simulation time 1520489805 ps
CPU time 4.33 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:29 PM PDT 24
Peak memory 204692 kb
Host smart-55d5fe38-5575-4bf8-9e77-2f67d469431d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531948097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2531948097
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2135330244
Short name T59
Test name
Test status
Simulation time 2030556762 ps
CPU time 6.38 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:31 PM PDT 24
Peak memory 229016 kb
Host smart-cb3819a2-a7f4-4be1-9570-36349a7ec8c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135330244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2135330244
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1361461332
Short name T214
Test name
Test status
Simulation time 1052220071 ps
CPU time 1.89 seconds
Started Jun 26 06:58:18 PM PDT 24
Finished Jun 26 06:58:23 PM PDT 24
Peak memory 204776 kb
Host smart-a6c0c59c-f6ad-4e8c-9dcd-ba424bcdcb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361461332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1361461332
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1193937767
Short name T34
Test name
Test status
Simulation time 7594511601 ps
CPU time 22.42 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:47 PM PDT 24
Peak memory 205240 kb
Host smart-0c23dd18-702b-4c36-b3ff-9387734ab704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193937767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1193937767
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.4206950239
Short name T212
Test name
Test status
Simulation time 157600573 ps
CPU time 1.15 seconds
Started Jun 26 06:58:41 PM PDT 24
Finished Jun 26 06:58:45 PM PDT 24
Peak memory 204996 kb
Host smart-b5ab008f-027f-491b-b96e-ddf464fcdea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206950239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.4206950239
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2406683236
Short name T199
Test name
Test status
Simulation time 3711774862 ps
CPU time 10.82 seconds
Started Jun 26 06:58:40 PM PDT 24
Finished Jun 26 06:58:53 PM PDT 24
Peak memory 205364 kb
Host smart-441329fc-f106-4e7d-94b0-241d718bea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406683236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2406683236
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2490534063
Short name T247
Test name
Test status
Simulation time 1731244027 ps
CPU time 2.34 seconds
Started Jun 26 06:58:41 PM PDT 24
Finished Jun 26 06:58:46 PM PDT 24
Peak memory 205316 kb
Host smart-4f8389ac-c610-4adc-913d-5a9ff48226ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490534063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2490534063
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1955539841
Short name T275
Test name
Test status
Simulation time 3918526351 ps
CPU time 5.87 seconds
Started Jun 26 06:58:40 PM PDT 24
Finished Jun 26 06:58:48 PM PDT 24
Peak memory 205432 kb
Host smart-70921367-564f-4f27-a951-d1952fde5135
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955539841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1955539841
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.2812881128
Short name T8
Test name
Test status
Simulation time 3081216505 ps
CPU time 2.99 seconds
Started Jun 26 06:58:42 PM PDT 24
Finished Jun 26 06:58:48 PM PDT 24
Peak memory 205448 kb
Host smart-aad3adae-ecfe-49c7-82b4-a0884243c59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812881128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2812881128
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.338080713
Short name T23
Test name
Test status
Simulation time 7193141423 ps
CPU time 6.64 seconds
Started Jun 26 06:58:46 PM PDT 24
Finished Jun 26 06:58:54 PM PDT 24
Peak memory 213428 kb
Host smart-dac4f56e-5c75-41e0-b04e-ad4d32f12283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338080713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.338080713
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1430232364
Short name T77
Test name
Test status
Simulation time 205181058 ps
CPU time 1.21 seconds
Started Jun 26 06:58:45 PM PDT 24
Finished Jun 26 06:58:47 PM PDT 24
Peak memory 204632 kb
Host smart-069751ef-a98b-4d36-a054-7bd32f8baa8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430232364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1430232364
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3878122375
Short name T241
Test name
Test status
Simulation time 6011094645 ps
CPU time 6.92 seconds
Started Jun 26 06:58:43 PM PDT 24
Finished Jun 26 06:58:52 PM PDT 24
Peak memory 205432 kb
Host smart-a6b48fca-bfe3-4c6c-b64f-38b77f8e3c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878122375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3878122375
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2889145520
Short name T9
Test name
Test status
Simulation time 1805845121 ps
CPU time 2.14 seconds
Started Jun 26 06:58:41 PM PDT 24
Finished Jun 26 06:58:46 PM PDT 24
Peak memory 205312 kb
Host smart-023b6b1d-cf32-4794-a4a0-310cd872c07f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2889145520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2889145520
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.963145206
Short name T2
Test name
Test status
Simulation time 2864878594 ps
CPU time 7.54 seconds
Started Jun 26 06:58:45 PM PDT 24
Finished Jun 26 06:58:54 PM PDT 24
Peak memory 205204 kb
Host smart-b7421302-6a7f-4006-810e-4f8bd189f8c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963145206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.963145206
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.653087368
Short name T186
Test name
Test status
Simulation time 58076703 ps
CPU time 0.83 seconds
Started Jun 26 06:58:42 PM PDT 24
Finished Jun 26 06:58:45 PM PDT 24
Peak memory 205016 kb
Host smart-9c3c5c6b-6b84-46b1-a6e9-f55f9b540022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653087368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.653087368
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3691372102
Short name T28
Test name
Test status
Simulation time 29339479181 ps
CPU time 43.03 seconds
Started Jun 26 06:58:46 PM PDT 24
Finished Jun 26 06:59:30 PM PDT 24
Peak memory 213568 kb
Host smart-f0df171e-b6fa-4464-aaaf-ef5642fb9960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691372102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3691372102
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.390028489
Short name T213
Test name
Test status
Simulation time 3703367764 ps
CPU time 6.45 seconds
Started Jun 26 06:58:42 PM PDT 24
Finished Jun 26 06:58:51 PM PDT 24
Peak memory 205504 kb
Host smart-64bb58d0-12d7-4a02-852a-9ac75175dfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390028489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.390028489
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1743530370
Short name T243
Test name
Test status
Simulation time 701573181 ps
CPU time 2.76 seconds
Started Jun 26 06:58:42 PM PDT 24
Finished Jun 26 06:58:47 PM PDT 24
Peak memory 205316 kb
Host smart-20faa075-0aec-4afa-bd3a-f07c68426f28
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743530370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1743530370
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3517536403
Short name T192
Test name
Test status
Simulation time 1385538715 ps
CPU time 3.9 seconds
Started Jun 26 06:58:41 PM PDT 24
Finished Jun 26 06:58:47 PM PDT 24
Peak memory 205264 kb
Host smart-8bcf7e67-cd04-4fb9-9199-2353112bac43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517536403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3517536403
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2215227704
Short name T168
Test name
Test status
Simulation time 67104282 ps
CPU time 0.77 seconds
Started Jun 26 06:58:39 PM PDT 24
Finished Jun 26 06:58:41 PM PDT 24
Peak memory 204924 kb
Host smart-b897302a-8c2f-4b86-85fb-c98415445981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215227704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2215227704
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1838071487
Short name T258
Test name
Test status
Simulation time 10707339091 ps
CPU time 30.18 seconds
Started Jun 26 06:58:41 PM PDT 24
Finished Jun 26 06:59:13 PM PDT 24
Peak memory 213620 kb
Host smart-0772b90d-d4ba-4f68-a30a-5bfe310362d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838071487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1838071487
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1832741380
Short name T204
Test name
Test status
Simulation time 2469223343 ps
CPU time 7.36 seconds
Started Jun 26 06:58:40 PM PDT 24
Finished Jun 26 06:58:48 PM PDT 24
Peak memory 205412 kb
Host smart-785e4941-6031-4e84-b1c0-0bb2836c6545
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832741380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1832741380
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2394834646
Short name T269
Test name
Test status
Simulation time 4211832771 ps
CPU time 9.58 seconds
Started Jun 26 06:58:41 PM PDT 24
Finished Jun 26 06:58:52 PM PDT 24
Peak memory 205440 kb
Host smart-b53b7026-9627-49ac-8adc-c6048eff1936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394834646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2394834646
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2679401095
Short name T239
Test name
Test status
Simulation time 20340457033 ps
CPU time 29.7 seconds
Started Jun 26 06:58:43 PM PDT 24
Finished Jun 26 06:59:15 PM PDT 24
Peak memory 205172 kb
Host smart-418cfab8-6ae3-4033-9d2b-be598b2ec718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679401095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2679401095
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2461396422
Short name T164
Test name
Test status
Simulation time 71711302 ps
CPU time 0.72 seconds
Started Jun 26 06:58:42 PM PDT 24
Finished Jun 26 06:58:45 PM PDT 24
Peak memory 205008 kb
Host smart-1e3d533a-eb47-43b1-a19b-986612d671d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461396422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2461396422
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.322717760
Short name T225
Test name
Test status
Simulation time 7061744860 ps
CPU time 16.39 seconds
Started Jun 26 06:58:44 PM PDT 24
Finished Jun 26 06:59:02 PM PDT 24
Peak memory 205376 kb
Host smart-680238bd-444b-417c-938f-79d91532b173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322717760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.322717760
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1264811590
Short name T257
Test name
Test status
Simulation time 565250082 ps
CPU time 1.15 seconds
Started Jun 26 06:58:41 PM PDT 24
Finished Jun 26 06:58:44 PM PDT 24
Peak memory 205396 kb
Host smart-0bfacbef-595f-4d13-9054-336c8af5ea50
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1264811590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1264811590
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.459439292
Short name T242
Test name
Test status
Simulation time 1871587560 ps
CPU time 2.41 seconds
Started Jun 26 06:58:39 PM PDT 24
Finished Jun 26 06:58:43 PM PDT 24
Peak memory 205296 kb
Host smart-a1027915-fdf0-4ce6-b4d3-7704bb502b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459439292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.459439292
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.765070990
Short name T150
Test name
Test status
Simulation time 4405802010 ps
CPU time 4.94 seconds
Started Jun 26 06:58:41 PM PDT 24
Finished Jun 26 06:58:48 PM PDT 24
Peak memory 213388 kb
Host smart-3dfc4424-4eb0-4d90-b447-adaa950b6333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765070990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.765070990
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.4000724953
Short name T278
Test name
Test status
Simulation time 51872546 ps
CPU time 0.86 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:58:57 PM PDT 24
Peak memory 204960 kb
Host smart-5903912d-bbb8-4da6-8dec-90abe407ef14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000724953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.4000724953
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1291622600
Short name T188
Test name
Test status
Simulation time 2889063930 ps
CPU time 2.41 seconds
Started Jun 26 06:58:51 PM PDT 24
Finished Jun 26 06:58:56 PM PDT 24
Peak memory 205364 kb
Host smart-fb759249-8826-4514-8282-cb15884b941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291622600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1291622600
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2534082814
Short name T283
Test name
Test status
Simulation time 1439240047 ps
CPU time 5.35 seconds
Started Jun 26 06:58:51 PM PDT 24
Finished Jun 26 06:58:59 PM PDT 24
Peak memory 205276 kb
Host smart-7759f601-10e8-4a77-a134-fb346bfa6b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534082814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2534082814
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.339027704
Short name T233
Test name
Test status
Simulation time 9245235808 ps
CPU time 6.55 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:59:03 PM PDT 24
Peak memory 205316 kb
Host smart-a508b013-3bf5-4bcc-beff-4b39b164c68a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=339027704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.339027704
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1633046765
Short name T261
Test name
Test status
Simulation time 4605997788 ps
CPU time 13.62 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:59:11 PM PDT 24
Peak memory 205384 kb
Host smart-140d7759-aa2b-4c6d-a571-4fccd9b0c623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633046765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1633046765
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3398782760
Short name T130
Test name
Test status
Simulation time 90344537 ps
CPU time 0.75 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:58:56 PM PDT 24
Peak memory 205008 kb
Host smart-a6c61ae7-6dd7-4958-9362-96cc66af9b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398782760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3398782760
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3899014730
Short name T273
Test name
Test status
Simulation time 1475682619 ps
CPU time 5.45 seconds
Started Jun 26 06:58:51 PM PDT 24
Finished Jun 26 06:58:59 PM PDT 24
Peak memory 205328 kb
Host smart-602466ad-6632-483e-828c-8f5d3b7e2e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899014730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3899014730
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.325759427
Short name T10
Test name
Test status
Simulation time 1310042126 ps
CPU time 1.56 seconds
Started Jun 26 06:58:52 PM PDT 24
Finished Jun 26 06:58:56 PM PDT 24
Peak memory 205348 kb
Host smart-616c12fa-f1b5-49a9-ae9d-a4c826c53347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325759427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.325759427
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.967315367
Short name T268
Test name
Test status
Simulation time 5128237995 ps
CPU time 4.76 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:59:01 PM PDT 24
Peak memory 205388 kb
Host smart-a64c113b-392e-4ca2-9dd6-c72ee91cb830
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967315367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.967315367
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1042611518
Short name T282
Test name
Test status
Simulation time 1590492728 ps
CPU time 5.26 seconds
Started Jun 26 06:58:51 PM PDT 24
Finished Jun 26 06:58:58 PM PDT 24
Peak memory 205348 kb
Host smart-09f8a366-6986-42d3-abd9-177a6b286352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042611518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1042611518
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2203751287
Short name T279
Test name
Test status
Simulation time 38042971 ps
CPU time 0.75 seconds
Started Jun 26 06:58:54 PM PDT 24
Finished Jun 26 06:58:58 PM PDT 24
Peak memory 204976 kb
Host smart-e67d5fde-3cf8-4e40-9be5-b44b0cec15d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203751287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2203751287
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.4135648100
Short name T203
Test name
Test status
Simulation time 19122830819 ps
CPU time 13.1 seconds
Started Jun 26 06:58:52 PM PDT 24
Finished Jun 26 06:59:08 PM PDT 24
Peak memory 213568 kb
Host smart-5a062387-ba75-4682-8a0c-42b87f222974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135648100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.4135648100
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2780434976
Short name T284
Test name
Test status
Simulation time 9735099996 ps
CPU time 7.39 seconds
Started Jun 26 06:58:52 PM PDT 24
Finished Jun 26 06:59:02 PM PDT 24
Peak memory 205396 kb
Host smart-da0f9587-acc5-4444-99a5-d93e25e94c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780434976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2780434976
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3156658773
Short name T237
Test name
Test status
Simulation time 12539107371 ps
CPU time 17.64 seconds
Started Jun 26 06:58:54 PM PDT 24
Finished Jun 26 06:59:15 PM PDT 24
Peak memory 205420 kb
Host smart-2fe6a426-aaf4-401e-bfaf-1003bc3279c7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156658773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3156658773
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.4288517760
Short name T240
Test name
Test status
Simulation time 6491477722 ps
CPU time 3.97 seconds
Started Jun 26 06:58:51 PM PDT 24
Finished Jun 26 06:58:56 PM PDT 24
Peak memory 205348 kb
Host smart-5c0f9761-ff01-4a4c-b349-9274a5b4c999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288517760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.4288517760
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.315582917
Short name T22
Test name
Test status
Simulation time 4396532588 ps
CPU time 13.35 seconds
Started Jun 26 06:58:51 PM PDT 24
Finished Jun 26 06:59:06 PM PDT 24
Peak memory 205160 kb
Host smart-17cea826-e6c4-4e5f-ae5d-764114812adf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315582917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.315582917
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2767232418
Short name T181
Test name
Test status
Simulation time 182028934 ps
CPU time 0.87 seconds
Started Jun 26 06:58:52 PM PDT 24
Finished Jun 26 06:58:54 PM PDT 24
Peak memory 204988 kb
Host smart-bf1fe416-f697-4793-aa7e-bd61ecf0ecce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767232418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2767232418
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.212760652
Short name T281
Test name
Test status
Simulation time 5218872472 ps
CPU time 10.16 seconds
Started Jun 26 06:58:54 PM PDT 24
Finished Jun 26 06:59:07 PM PDT 24
Peak memory 213620 kb
Host smart-3ae3c211-1888-4286-b56b-9f81964fac02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212760652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.212760652
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1654429237
Short name T263
Test name
Test status
Simulation time 6470574382 ps
CPU time 4.89 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:59:01 PM PDT 24
Peak memory 205432 kb
Host smart-01e79229-386e-43c8-bf4a-23adf7d8dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654429237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1654429237
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1214526997
Short name T229
Test name
Test status
Simulation time 4981008096 ps
CPU time 6.43 seconds
Started Jun 26 06:58:56 PM PDT 24
Finished Jun 26 06:59:05 PM PDT 24
Peak memory 205376 kb
Host smart-ab87b3b9-7c1b-4004-ad6b-53aa50638c9f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214526997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1214526997
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.505699326
Short name T187
Test name
Test status
Simulation time 1761438652 ps
CPU time 1.74 seconds
Started Jun 26 06:58:51 PM PDT 24
Finished Jun 26 06:58:53 PM PDT 24
Peak memory 205288 kb
Host smart-382d4ee2-06f1-40d0-aa16-6cc43fe17f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505699326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.505699326
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.823945470
Short name T167
Test name
Test status
Simulation time 104467845 ps
CPU time 0.76 seconds
Started Jun 26 06:58:54 PM PDT 24
Finished Jun 26 06:58:58 PM PDT 24
Peak memory 205036 kb
Host smart-8347cf6b-094e-4c52-bc5d-971fd66a3a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823945470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.823945470
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1758829718
Short name T256
Test name
Test status
Simulation time 4781222618 ps
CPU time 4.84 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:59:01 PM PDT 24
Peak memory 205452 kb
Host smart-fcadf047-8351-4acd-84f6-fb808d6895f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758829718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1758829718
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.707919683
Short name T254
Test name
Test status
Simulation time 1990264528 ps
CPU time 6.47 seconds
Started Jun 26 06:58:52 PM PDT 24
Finished Jun 26 06:59:01 PM PDT 24
Peak memory 205292 kb
Host smart-0d324190-5184-429a-bd6d-a139a7996581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707919683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.707919683
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1057280800
Short name T228
Test name
Test status
Simulation time 1492702583 ps
CPU time 4.98 seconds
Started Jun 26 06:58:54 PM PDT 24
Finished Jun 26 06:59:03 PM PDT 24
Peak memory 205256 kb
Host smart-f7d2243b-bee4-4898-b98d-e8b978f425a9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057280800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1057280800
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2085858452
Short name T190
Test name
Test status
Simulation time 2260345923 ps
CPU time 6.73 seconds
Started Jun 26 06:58:52 PM PDT 24
Finished Jun 26 06:59:01 PM PDT 24
Peak memory 205420 kb
Host smart-286b805b-5ba4-430d-82fa-4172d4189bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085858452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2085858452
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.938956171
Short name T171
Test name
Test status
Simulation time 134434785 ps
CPU time 1 seconds
Started Jun 26 06:58:33 PM PDT 24
Finished Jun 26 06:58:36 PM PDT 24
Peak memory 204992 kb
Host smart-b291e0d7-e5cb-4cb6-8b21-76c09b3f4aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938956171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.938956171
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2985959403
Short name T29
Test name
Test status
Simulation time 29387348244 ps
CPU time 91.65 seconds
Started Jun 26 06:58:31 PM PDT 24
Finished Jun 26 07:00:05 PM PDT 24
Peak memory 213656 kb
Host smart-ad438775-d053-4879-9700-5fa54cf43182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985959403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2985959403
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.70646922
Short name T262
Test name
Test status
Simulation time 6217702427 ps
CPU time 11.78 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:36 PM PDT 24
Peak memory 213596 kb
Host smart-2a10716d-4557-49f8-981a-108568d54caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70646922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.70646922
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1975624248
Short name T218
Test name
Test status
Simulation time 1867028745 ps
CPU time 2.25 seconds
Started Jun 26 06:58:21 PM PDT 24
Finished Jun 26 06:58:27 PM PDT 24
Peak memory 205320 kb
Host smart-df44f166-6043-4e3e-8469-44c12ca2eabb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1975624248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1975624248
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1705527904
Short name T222
Test name
Test status
Simulation time 242565574 ps
CPU time 1.2 seconds
Started Jun 26 06:58:28 PM PDT 24
Finished Jun 26 06:58:31 PM PDT 24
Peak memory 204796 kb
Host smart-f8badec9-0228-44be-bbd5-55a8c1ae0fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705527904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1705527904
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.2429452205
Short name T211
Test name
Test status
Simulation time 4853702675 ps
CPU time 13.42 seconds
Started Jun 26 06:58:20 PM PDT 24
Finished Jun 26 06:58:37 PM PDT 24
Peak memory 205384 kb
Host smart-64032902-4735-4fd4-8c25-0d8610295d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429452205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2429452205
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2216770048
Short name T71
Test name
Test status
Simulation time 458296277 ps
CPU time 1.51 seconds
Started Jun 26 06:58:30 PM PDT 24
Finished Jun 26 06:58:34 PM PDT 24
Peak memory 237432 kb
Host smart-31ad9e8f-af9b-42bf-b70d-6ca0e155b6fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216770048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2216770048
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.1581523411
Short name T206
Test name
Test status
Simulation time 5351378476 ps
CPU time 4.42 seconds
Started Jun 26 06:58:30 PM PDT 24
Finished Jun 26 06:58:37 PM PDT 24
Peak memory 213484 kb
Host smart-3ec78cd8-8581-4942-ab9f-72c509e6d199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581523411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1581523411
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.448825925
Short name T124
Test name
Test status
Simulation time 68561948 ps
CPU time 0.75 seconds
Started Jun 26 06:58:52 PM PDT 24
Finished Jun 26 06:58:56 PM PDT 24
Peak memory 205032 kb
Host smart-3e0d9e55-b3ef-4b22-ad7c-275132637030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448825925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.448825925
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2404471299
Short name T6
Test name
Test status
Simulation time 7963348336 ps
CPU time 5.32 seconds
Started Jun 26 06:58:54 PM PDT 24
Finished Jun 26 06:59:03 PM PDT 24
Peak memory 205220 kb
Host smart-6f472976-0d0e-41d2-8808-ff311377fbdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404471299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2404471299
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1230932627
Short name T44
Test name
Test status
Simulation time 72361764 ps
CPU time 1 seconds
Started Jun 26 06:58:52 PM PDT 24
Finished Jun 26 06:58:55 PM PDT 24
Peak memory 204984 kb
Host smart-898cb00e-f49d-4dc0-bee3-9fd7558987ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230932627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1230932627
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3493817164
Short name T286
Test name
Test status
Simulation time 3357644021 ps
CPU time 9.81 seconds
Started Jun 26 06:58:56 PM PDT 24
Finished Jun 26 06:59:09 PM PDT 24
Peak memory 205212 kb
Host smart-52994b4a-96be-4afb-b995-a3891464b380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493817164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3493817164
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.870168866
Short name T76
Test name
Test status
Simulation time 139194534 ps
CPU time 0.75 seconds
Started Jun 26 06:58:52 PM PDT 24
Finished Jun 26 06:58:55 PM PDT 24
Peak memory 204988 kb
Host smart-2147b8bf-a742-49f2-8a6e-b6257f8de224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870168866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.870168866
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3937094172
Short name T3
Test name
Test status
Simulation time 14106542540 ps
CPU time 10.05 seconds
Started Jun 26 06:58:56 PM PDT 24
Finished Jun 26 06:59:09 PM PDT 24
Peak memory 205384 kb
Host smart-9d62657a-986f-451e-b921-0e2d81afbfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937094172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3937094172
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.817726125
Short name T74
Test name
Test status
Simulation time 90715395 ps
CPU time 0.79 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:58:57 PM PDT 24
Peak memory 205020 kb
Host smart-9d3d7b94-dddf-4795-8959-19a6e8b2efae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817726125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.817726125
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.4047381059
Short name T154
Test name
Test status
Simulation time 7414667125 ps
CPU time 20.67 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:59:17 PM PDT 24
Peak memory 205212 kb
Host smart-05671b4b-ab27-48ea-95d5-46c69e76a245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047381059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.4047381059
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1773092351
Short name T180
Test name
Test status
Simulation time 93790883 ps
CPU time 0.78 seconds
Started Jun 26 06:58:52 PM PDT 24
Finished Jun 26 06:58:54 PM PDT 24
Peak memory 205012 kb
Host smart-2dae4d16-0b65-430b-aada-ac92353f28fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773092351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1773092351
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.880750495
Short name T195
Test name
Test status
Simulation time 8778715728 ps
CPU time 28.3 seconds
Started Jun 26 06:58:57 PM PDT 24
Finished Jun 26 06:59:27 PM PDT 24
Peak memory 205296 kb
Host smart-62341d0b-b63e-4b29-afd7-998d24f8a915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880750495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.880750495
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.4253349224
Short name T178
Test name
Test status
Simulation time 76863711 ps
CPU time 0.9 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:58:57 PM PDT 24
Peak memory 205008 kb
Host smart-5c01353e-9396-4654-b353-afb912f17086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253349224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.4253349224
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.4260232635
Short name T232
Test name
Test status
Simulation time 9971976786 ps
CPU time 25.48 seconds
Started Jun 26 06:58:54 PM PDT 24
Finished Jun 26 06:59:23 PM PDT 24
Peak memory 205276 kb
Host smart-1aeaca21-4d46-4953-b735-d39c403a1ff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260232635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.4260232635
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3339776435
Short name T87
Test name
Test status
Simulation time 45366652 ps
CPU time 0.82 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:58:57 PM PDT 24
Peak memory 204904 kb
Host smart-074689e0-3cd2-49a3-94aa-396e3970a8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339776435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3339776435
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1565514203
Short name T185
Test name
Test status
Simulation time 39283402 ps
CPU time 0.69 seconds
Started Jun 26 06:58:54 PM PDT 24
Finished Jun 26 06:58:58 PM PDT 24
Peak memory 205008 kb
Host smart-7ad9f13c-39bf-4b3f-906a-5d910705a8d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565514203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1565514203
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.4128574283
Short name T209
Test name
Test status
Simulation time 7089331051 ps
CPU time 3.04 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:58:59 PM PDT 24
Peak memory 205232 kb
Host smart-590218b2-2e3b-4663-afbd-c7b7d7c76d4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128574283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.4128574283
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.290932236
Short name T179
Test name
Test status
Simulation time 75339647 ps
CPU time 0.77 seconds
Started Jun 26 06:58:50 PM PDT 24
Finished Jun 26 06:58:52 PM PDT 24
Peak memory 204992 kb
Host smart-b63d6612-4434-4c90-aa27-93292eab1e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290932236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.290932236
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2412500439
Short name T143
Test name
Test status
Simulation time 7294593816 ps
CPU time 21.09 seconds
Started Jun 26 06:58:56 PM PDT 24
Finished Jun 26 06:59:20 PM PDT 24
Peak memory 221808 kb
Host smart-0b9264d8-6981-4fb9-95b8-8022ed952567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412500439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2412500439
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1727088754
Short name T244
Test name
Test status
Simulation time 71598776 ps
CPU time 0.77 seconds
Started Jun 26 06:58:56 PM PDT 24
Finished Jun 26 06:59:00 PM PDT 24
Peak memory 205220 kb
Host smart-b5519b15-fb0f-485b-980d-d1f85bb008ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727088754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1727088754
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.3681974911
Short name T151
Test name
Test status
Simulation time 2388308552 ps
CPU time 4.35 seconds
Started Jun 26 06:58:54 PM PDT 24
Finished Jun 26 06:59:02 PM PDT 24
Peak memory 205224 kb
Host smart-189ee384-5eba-4888-8957-8a42615e613e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681974911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3681974911
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2516890815
Short name T260
Test name
Test status
Simulation time 3637899635 ps
CPU time 7.02 seconds
Started Jun 26 06:58:31 PM PDT 24
Finished Jun 26 06:58:41 PM PDT 24
Peak memory 205460 kb
Host smart-413dd77a-eacc-43ff-aff5-1d80c71b9842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516890815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2516890815
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1731890143
Short name T266
Test name
Test status
Simulation time 9579888377 ps
CPU time 7.42 seconds
Started Jun 26 06:58:31 PM PDT 24
Finished Jun 26 06:58:41 PM PDT 24
Peak memory 213644 kb
Host smart-141a313b-258b-4517-a087-777bcfd00a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731890143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1731890143
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2805358793
Short name T271
Test name
Test status
Simulation time 1383727812 ps
CPU time 1.64 seconds
Started Jun 26 06:58:29 PM PDT 24
Finished Jun 26 06:58:33 PM PDT 24
Peak memory 205236 kb
Host smart-46ee568b-e1a4-41cc-8099-281fa4bbaafe
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805358793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2805358793
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1626630541
Short name T251
Test name
Test status
Simulation time 863621253 ps
CPU time 0.99 seconds
Started Jun 26 06:58:31 PM PDT 24
Finished Jun 26 06:58:34 PM PDT 24
Peak memory 204784 kb
Host smart-af3d2341-8c90-44b8-bfe4-5fe742deb212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626630541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1626630541
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.46278563
Short name T238
Test name
Test status
Simulation time 3329891675 ps
CPU time 5.37 seconds
Started Jun 26 06:59:12 PM PDT 24
Finished Jun 26 06:59:18 PM PDT 24
Peak memory 205428 kb
Host smart-eebef556-9243-4f72-905a-c7b16242f03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46278563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.46278563
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3784834761
Short name T43
Test name
Test status
Simulation time 470706042 ps
CPU time 1.3 seconds
Started Jun 26 06:58:28 PM PDT 24
Finished Jun 26 06:58:31 PM PDT 24
Peak memory 237392 kb
Host smart-b4359854-c67e-4464-8f31-034695bc48e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784834761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3784834761
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.3597001680
Short name T221
Test name
Test status
Simulation time 13301998837 ps
CPU time 37.23 seconds
Started Jun 26 06:58:30 PM PDT 24
Finished Jun 26 06:59:09 PM PDT 24
Peak memory 205228 kb
Host smart-1244e82e-67f8-4346-80b4-16df59b47182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597001680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3597001680
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.4262557133
Short name T175
Test name
Test status
Simulation time 89781478 ps
CPU time 0.77 seconds
Started Jun 26 06:58:54 PM PDT 24
Finished Jun 26 06:58:58 PM PDT 24
Peak memory 205008 kb
Host smart-89515d03-50f0-47c4-8e5e-2ba473d1691e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262557133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.4262557133
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3857413203
Short name T165
Test name
Test status
Simulation time 42168129 ps
CPU time 0.87 seconds
Started Jun 26 06:58:54 PM PDT 24
Finished Jun 26 06:58:58 PM PDT 24
Peak memory 205000 kb
Host smart-6e0474c3-4a5c-4559-b139-c7162b753f65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857413203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3857413203
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.869050053
Short name T196
Test name
Test status
Simulation time 4671568240 ps
CPU time 14.91 seconds
Started Jun 26 06:58:53 PM PDT 24
Finished Jun 26 06:59:11 PM PDT 24
Peak memory 205284 kb
Host smart-01409714-2864-4bde-82f7-1559ddb1a897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869050053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.869050053
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2313081105
Short name T176
Test name
Test status
Simulation time 71894317 ps
CPU time 0.76 seconds
Started Jun 26 06:59:05 PM PDT 24
Finished Jun 26 06:59:07 PM PDT 24
Peak memory 205036 kb
Host smart-70d03526-83d9-4317-9db3-a520bdc1b108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313081105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2313081105
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.3564254924
Short name T149
Test name
Test status
Simulation time 9328037018 ps
CPU time 13.51 seconds
Started Jun 26 06:59:04 PM PDT 24
Finished Jun 26 06:59:18 PM PDT 24
Peak memory 205244 kb
Host smart-b4a6e5e8-1d1e-4524-b5f8-8fe4737e21dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564254924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3564254924
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1956542001
Short name T169
Test name
Test status
Simulation time 146777121 ps
CPU time 0.91 seconds
Started Jun 26 06:59:05 PM PDT 24
Finished Jun 26 06:59:08 PM PDT 24
Peak memory 204996 kb
Host smart-0a56fd2d-9b43-406b-a4db-c90f5e3f8801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956542001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1956542001
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1651834337
Short name T182
Test name
Test status
Simulation time 142733095 ps
CPU time 0.92 seconds
Started Jun 26 06:59:05 PM PDT 24
Finished Jun 26 06:59:08 PM PDT 24
Peak memory 205020 kb
Host smart-b1a89777-57b6-41a7-b61e-cfbcbd4ba24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651834337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1651834337
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.3795071747
Short name T31
Test name
Test status
Simulation time 10076556992 ps
CPU time 17.55 seconds
Started Jun 26 06:59:05 PM PDT 24
Finished Jun 26 06:59:25 PM PDT 24
Peak memory 213452 kb
Host smart-4dc2cf71-6e05-4bb8-93fb-576a41b3e454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795071747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3795071747
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3596170270
Short name T162
Test name
Test status
Simulation time 38110058 ps
CPU time 0.79 seconds
Started Jun 26 06:59:04 PM PDT 24
Finished Jun 26 06:59:06 PM PDT 24
Peak memory 204988 kb
Host smart-0af4a317-8d03-4f44-9f66-7ddb74a7c680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596170270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3596170270
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2532422997
Short name T7
Test name
Test status
Simulation time 3110679332 ps
CPU time 8.36 seconds
Started Jun 26 06:59:07 PM PDT 24
Finished Jun 26 06:59:18 PM PDT 24
Peak memory 205284 kb
Host smart-9703321f-15fc-4f2f-a992-17064567a71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532422997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2532422997
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2844599386
Short name T68
Test name
Test status
Simulation time 59644783 ps
CPU time 0.73 seconds
Started Jun 26 06:59:07 PM PDT 24
Finished Jun 26 06:59:10 PM PDT 24
Peak memory 204964 kb
Host smart-d8d0bda7-44e9-4313-b884-34f1e16d95b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844599386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2844599386
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.647636791
Short name T131
Test name
Test status
Simulation time 6704046421 ps
CPU time 10.69 seconds
Started Jun 26 06:59:02 PM PDT 24
Finished Jun 26 06:59:14 PM PDT 24
Peak memory 213408 kb
Host smart-8777375a-9121-4183-98d0-77d1866aafa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647636791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.647636791
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1376794954
Short name T184
Test name
Test status
Simulation time 92904286 ps
CPU time 0.73 seconds
Started Jun 26 06:59:06 PM PDT 24
Finished Jun 26 06:59:10 PM PDT 24
Peak memory 205036 kb
Host smart-bcc4781c-7e0c-492d-91f3-7f502313d922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376794954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1376794954
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.58579621
Short name T146
Test name
Test status
Simulation time 3956512166 ps
CPU time 12.18 seconds
Started Jun 26 06:59:07 PM PDT 24
Finished Jun 26 06:59:22 PM PDT 24
Peak memory 213356 kb
Host smart-22bfe61e-464d-47a4-a5b4-33d1a880d3f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58579621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.58579621
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3135977474
Short name T226
Test name
Test status
Simulation time 93247988 ps
CPU time 0.81 seconds
Started Jun 26 06:59:06 PM PDT 24
Finished Jun 26 06:59:09 PM PDT 24
Peak memory 205008 kb
Host smart-8c0eee55-6c3b-4af8-b8c9-200f6cb89952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135977474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3135977474
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3865294485
Short name T220
Test name
Test status
Simulation time 9689621628 ps
CPU time 25.89 seconds
Started Jun 26 06:59:06 PM PDT 24
Finished Jun 26 06:59:33 PM PDT 24
Peak memory 205292 kb
Host smart-4e87763b-eade-4530-878a-4ed99142854a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865294485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3865294485
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2212102391
Short name T197
Test name
Test status
Simulation time 120423725 ps
CPU time 0.92 seconds
Started Jun 26 06:59:09 PM PDT 24
Finished Jun 26 06:59:11 PM PDT 24
Peak memory 204924 kb
Host smart-92cdb8a8-4eb4-4525-864e-6ed3753de9bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212102391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2212102391
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3546531178
Short name T132
Test name
Test status
Simulation time 2650297432 ps
CPU time 2.8 seconds
Started Jun 26 06:59:06 PM PDT 24
Finished Jun 26 06:59:11 PM PDT 24
Peak memory 205332 kb
Host smart-d606c22b-6bed-4788-ae70-95c62be34fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546531178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3546531178
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1933653618
Short name T170
Test name
Test status
Simulation time 81906827 ps
CPU time 0.89 seconds
Started Jun 26 06:58:29 PM PDT 24
Finished Jun 26 06:58:33 PM PDT 24
Peak memory 205012 kb
Host smart-55e38e46-5049-49a5-828f-9244bf0ad166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933653618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1933653618
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2040511120
Short name T215
Test name
Test status
Simulation time 68897558734 ps
CPU time 44.66 seconds
Started Jun 26 06:58:29 PM PDT 24
Finished Jun 26 06:59:17 PM PDT 24
Peak memory 215056 kb
Host smart-1a053262-311e-4dab-bfca-c27e3fd9a86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040511120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2040511120
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2182559241
Short name T24
Test name
Test status
Simulation time 2468573254 ps
CPU time 6.69 seconds
Started Jun 26 06:58:27 PM PDT 24
Finished Jun 26 06:58:35 PM PDT 24
Peak memory 205372 kb
Host smart-86dc0760-b167-40dd-941b-b7ad09cb978f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182559241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2182559241
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.863516610
Short name T193
Test name
Test status
Simulation time 7425724867 ps
CPU time 22.36 seconds
Started Jun 26 06:58:28 PM PDT 24
Finished Jun 26 06:58:52 PM PDT 24
Peak memory 205372 kb
Host smart-214b080d-cebe-4d42-a0ca-ab519a7aadbf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=863516610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.863516610
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.467082224
Short name T236
Test name
Test status
Simulation time 111119533 ps
CPU time 0.72 seconds
Started Jun 26 06:58:30 PM PDT 24
Finished Jun 26 06:58:34 PM PDT 24
Peak memory 204788 kb
Host smart-21cb5d32-cd2a-4d1c-bda0-72b61f029ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467082224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.467082224
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1757250958
Short name T270
Test name
Test status
Simulation time 1830599785 ps
CPU time 2.77 seconds
Started Jun 26 06:58:29 PM PDT 24
Finished Jun 26 06:58:35 PM PDT 24
Peak memory 205300 kb
Host smart-88f05877-c100-4068-8771-a007674a26b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757250958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1757250958
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1852638977
Short name T70
Test name
Test status
Simulation time 340638377 ps
CPU time 1.87 seconds
Started Jun 26 06:58:30 PM PDT 24
Finished Jun 26 06:58:34 PM PDT 24
Peak memory 236464 kb
Host smart-dada0fef-bff4-462d-ba26-fa2bbda30673
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852638977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1852638977
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.3440474334
Short name T20
Test name
Test status
Simulation time 13085677927 ps
CPU time 11.24 seconds
Started Jun 26 06:58:27 PM PDT 24
Finished Jun 26 06:58:40 PM PDT 24
Peak memory 205284 kb
Host smart-02878320-2c31-48fe-8e01-8509b4895763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440474334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3440474334
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.615754623
Short name T172
Test name
Test status
Simulation time 95625890 ps
CPU time 0.95 seconds
Started Jun 26 06:59:07 PM PDT 24
Finished Jun 26 06:59:11 PM PDT 24
Peak memory 205028 kb
Host smart-8867015a-4c9c-4aa9-9b9d-ef0a78763503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615754623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.615754623
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3094085606
Short name T248
Test name
Test status
Simulation time 45397365 ps
CPU time 0.79 seconds
Started Jun 26 06:59:04 PM PDT 24
Finished Jun 26 06:59:06 PM PDT 24
Peak memory 205004 kb
Host smart-58f31e24-5a63-46b9-a165-c81e0f2b3981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094085606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3094085606
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3388506177
Short name T147
Test name
Test status
Simulation time 12060511282 ps
CPU time 4.7 seconds
Started Jun 26 06:59:04 PM PDT 24
Finished Jun 26 06:59:11 PM PDT 24
Peak memory 205204 kb
Host smart-f71ef336-41dd-4e3c-b5f8-efa8b2e31ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388506177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3388506177
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2349684801
Short name T216
Test name
Test status
Simulation time 101689169 ps
CPU time 0.84 seconds
Started Jun 26 06:59:12 PM PDT 24
Finished Jun 26 06:59:13 PM PDT 24
Peak memory 205004 kb
Host smart-ae90980e-3afb-46ad-8a98-cf477d515adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349684801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2349684801
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.1250983492
Short name T26
Test name
Test status
Simulation time 8835508715 ps
CPU time 7.43 seconds
Started Jun 26 06:59:05 PM PDT 24
Finished Jun 26 06:59:13 PM PDT 24
Peak memory 213468 kb
Host smart-09501a97-5bad-4643-b5f3-44159a9b0fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250983492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1250983492
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1911680537
Short name T41
Test name
Test status
Simulation time 176856862 ps
CPU time 0.94 seconds
Started Jun 26 06:59:07 PM PDT 24
Finished Jun 26 06:59:10 PM PDT 24
Peak memory 205004 kb
Host smart-d9fc54f0-a143-4247-a342-350c8d9551cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911680537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1911680537
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.1983325833
Short name T5
Test name
Test status
Simulation time 2734224122 ps
CPU time 7.72 seconds
Started Jun 26 06:59:04 PM PDT 24
Finished Jun 26 06:59:13 PM PDT 24
Peak memory 205236 kb
Host smart-54d6b877-30e0-424b-ac10-3e22614fc51b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983325833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1983325833
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1844026506
Short name T75
Test name
Test status
Simulation time 72733840 ps
CPU time 0.77 seconds
Started Jun 26 06:59:06 PM PDT 24
Finished Jun 26 06:59:09 PM PDT 24
Peak memory 205012 kb
Host smart-f7b57455-84c7-45bb-b6ef-7a440fe547b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844026506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1844026506
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.4007776784
Short name T145
Test name
Test status
Simulation time 2252901441 ps
CPU time 6.91 seconds
Started Jun 26 06:59:06 PM PDT 24
Finished Jun 26 06:59:16 PM PDT 24
Peak memory 205296 kb
Host smart-8e922ad8-7409-460f-aa26-efbf9a576662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007776784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.4007776784
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.803098543
Short name T183
Test name
Test status
Simulation time 72840749 ps
CPU time 0.72 seconds
Started Jun 26 06:59:05 PM PDT 24
Finished Jun 26 06:59:08 PM PDT 24
Peak memory 205012 kb
Host smart-b223ada1-7e92-4c42-a067-13a5fca4c5c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803098543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.803098543
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.2484552848
Short name T152
Test name
Test status
Simulation time 8151049959 ps
CPU time 4.77 seconds
Started Jun 26 06:59:06 PM PDT 24
Finished Jun 26 06:59:13 PM PDT 24
Peak memory 205296 kb
Host smart-04739e8d-e434-4ebc-9737-6acfa4ad91e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484552848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2484552848
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2603946966
Short name T166
Test name
Test status
Simulation time 51334192 ps
CPU time 0.81 seconds
Started Jun 26 06:59:07 PM PDT 24
Finished Jun 26 06:59:10 PM PDT 24
Peak memory 204976 kb
Host smart-53eaa35f-9a37-4f68-8c08-daa69d06a4ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603946966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2603946966
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2791472469
Short name T148
Test name
Test status
Simulation time 5180921863 ps
CPU time 15.44 seconds
Started Jun 26 06:59:05 PM PDT 24
Finished Jun 26 06:59:23 PM PDT 24
Peak memory 205428 kb
Host smart-cab72f58-a3e9-4f35-93bf-a0e6f0b0ec2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791472469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2791472469
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3563705730
Short name T267
Test name
Test status
Simulation time 81728875 ps
CPU time 0.87 seconds
Started Jun 26 06:59:06 PM PDT 24
Finished Jun 26 06:59:09 PM PDT 24
Peak memory 204984 kb
Host smart-e032f626-8604-4b83-bde3-3df9c96aa845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563705730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3563705730
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3037209899
Short name T235
Test name
Test status
Simulation time 4770137964 ps
CPU time 12.93 seconds
Started Jun 26 06:59:06 PM PDT 24
Finished Jun 26 06:59:21 PM PDT 24
Peak memory 205208 kb
Host smart-0751e4da-40c6-438e-8b52-46034d93f57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037209899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3037209899
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1098572906
Short name T161
Test name
Test status
Simulation time 148874686 ps
CPU time 0.73 seconds
Started Jun 26 06:59:17 PM PDT 24
Finished Jun 26 06:59:19 PM PDT 24
Peak memory 205024 kb
Host smart-65260066-06a3-4847-80fd-66154385d322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098572906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1098572906
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.2411350221
Short name T155
Test name
Test status
Simulation time 8428096757 ps
CPU time 25.29 seconds
Started Jun 26 06:59:18 PM PDT 24
Finished Jun 26 06:59:46 PM PDT 24
Peak memory 205316 kb
Host smart-5bb1f188-4098-488c-acdd-8a2b2782d327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411350221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2411350221
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3914788604
Short name T177
Test name
Test status
Simulation time 125035621 ps
CPU time 0.75 seconds
Started Jun 26 06:58:28 PM PDT 24
Finished Jun 26 06:58:31 PM PDT 24
Peak memory 205016 kb
Host smart-19080d06-e2b7-4105-b435-770c6c6b3f1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914788604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3914788604
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1231074531
Short name T245
Test name
Test status
Simulation time 17942798623 ps
CPU time 17.87 seconds
Started Jun 26 06:58:29 PM PDT 24
Finished Jun 26 06:58:50 PM PDT 24
Peak memory 213640 kb
Host smart-8c61bf29-08d4-4dbf-9a35-4bacc603b222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231074531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1231074531
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2132750196
Short name T272
Test name
Test status
Simulation time 3988066295 ps
CPU time 11.3 seconds
Started Jun 26 06:58:27 PM PDT 24
Finished Jun 26 06:58:40 PM PDT 24
Peak memory 205380 kb
Host smart-2189d517-77f6-41d5-be91-e4661bfb5b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132750196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2132750196
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2598019786
Short name T69
Test name
Test status
Simulation time 3679094071 ps
CPU time 4.13 seconds
Started Jun 26 06:58:32 PM PDT 24
Finished Jun 26 06:58:39 PM PDT 24
Peak memory 205456 kb
Host smart-ca377128-0f15-4d6d-ac46-c4e2d033f20d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2598019786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2598019786
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1139872784
Short name T205
Test name
Test status
Simulation time 6489137470 ps
CPU time 9.88 seconds
Started Jun 26 06:58:27 PM PDT 24
Finished Jun 26 06:58:38 PM PDT 24
Peak memory 205404 kb
Host smart-6a83f4b1-2ea4-49f2-bd83-5efa96174f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139872784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1139872784
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1076100133
Short name T36
Test name
Test status
Simulation time 138126834 ps
CPU time 0.99 seconds
Started Jun 26 06:58:31 PM PDT 24
Finished Jun 26 06:58:34 PM PDT 24
Peak memory 205020 kb
Host smart-dc0bca4b-6a39-4e38-b5e3-39e7e7b4ab7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076100133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1076100133
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1239546164
Short name T194
Test name
Test status
Simulation time 2566884298 ps
CPU time 6.95 seconds
Started Jun 26 06:58:32 PM PDT 24
Finished Jun 26 06:58:41 PM PDT 24
Peak memory 205440 kb
Host smart-5d4ee458-18ad-409b-9a24-07b43afb6c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239546164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1239546164
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1705298029
Short name T208
Test name
Test status
Simulation time 1994289595 ps
CPU time 2.3 seconds
Started Jun 26 06:58:30 PM PDT 24
Finished Jun 26 06:58:35 PM PDT 24
Peak memory 205320 kb
Host smart-dd7ba593-7484-4e47-a115-4f3fc6412fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705298029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1705298029
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2195315358
Short name T200
Test name
Test status
Simulation time 9138572697 ps
CPU time 26.25 seconds
Started Jun 26 06:58:30 PM PDT 24
Finished Jun 26 06:58:59 PM PDT 24
Peak memory 205488 kb
Host smart-7f06ad64-2b10-4a1e-a793-11f5508c3e16
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195315358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2195315358
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1947876254
Short name T45
Test name
Test status
Simulation time 3718997631 ps
CPU time 6.55 seconds
Started Jun 26 06:58:27 PM PDT 24
Finished Jun 26 06:58:35 PM PDT 24
Peak memory 205356 kb
Host smart-50b25496-8e5e-40eb-8110-7751a50a3825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947876254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1947876254
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.2107964102
Short name T32
Test name
Test status
Simulation time 4122294061 ps
CPU time 11.93 seconds
Started Jun 26 06:58:33 PM PDT 24
Finished Jun 26 06:58:47 PM PDT 24
Peak memory 205272 kb
Host smart-df0b4a54-8175-4d68-bab5-68ab7175a8c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107964102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2107964102
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2473453704
Short name T202
Test name
Test status
Simulation time 195468707 ps
CPU time 0.82 seconds
Started Jun 26 06:58:30 PM PDT 24
Finished Jun 26 06:58:33 PM PDT 24
Peak memory 205016 kb
Host smart-18559b36-5a15-4eef-822f-e2141e54b792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473453704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2473453704
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1081026984
Short name T223
Test name
Test status
Simulation time 2976365996 ps
CPU time 2.74 seconds
Started Jun 26 06:58:32 PM PDT 24
Finished Jun 26 06:58:37 PM PDT 24
Peak memory 205468 kb
Host smart-4c10ccc9-c988-45d5-9935-3cb7ef7496f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081026984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1081026984
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1086941201
Short name T265
Test name
Test status
Simulation time 2787624995 ps
CPU time 4.59 seconds
Started Jun 26 06:58:30 PM PDT 24
Finished Jun 26 06:58:38 PM PDT 24
Peak memory 205372 kb
Host smart-2c7a151b-4473-4cf6-9e66-5d6e8ce3adbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086941201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1086941201
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3328625569
Short name T207
Test name
Test status
Simulation time 3142090989 ps
CPU time 9.65 seconds
Started Jun 26 06:58:29 PM PDT 24
Finished Jun 26 06:58:42 PM PDT 24
Peak memory 205384 kb
Host smart-7e498551-df59-4e7e-94e9-491dfe64877d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328625569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3328625569
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1423114972
Short name T252
Test name
Test status
Simulation time 1646954907 ps
CPU time 2.46 seconds
Started Jun 26 06:58:34 PM PDT 24
Finished Jun 26 06:58:38 PM PDT 24
Peak memory 205272 kb
Host smart-ab832b3d-444f-4268-a174-70874c9426ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423114972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1423114972
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.3678722897
Short name T142
Test name
Test status
Simulation time 5699825776 ps
CPU time 9.71 seconds
Started Jun 26 06:58:32 PM PDT 24
Finished Jun 26 06:58:44 PM PDT 24
Peak memory 205292 kb
Host smart-6a90ffda-3758-4df7-ab0e-04317acb7742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678722897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3678722897
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3222531896
Short name T231
Test name
Test status
Simulation time 56815546 ps
CPU time 0.75 seconds
Started Jun 26 06:58:40 PM PDT 24
Finished Jun 26 06:58:43 PM PDT 24
Peak memory 204976 kb
Host smart-2ac2343b-f006-472c-a038-4886423683b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222531896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3222531896
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2963561976
Short name T259
Test name
Test status
Simulation time 7890606050 ps
CPU time 12.08 seconds
Started Jun 26 06:58:40 PM PDT 24
Finished Jun 26 06:58:54 PM PDT 24
Peak memory 213852 kb
Host smart-ec4f27e5-3690-437e-a7d4-1c522349e2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963561976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2963561976
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2430143286
Short name T253
Test name
Test status
Simulation time 6260173685 ps
CPU time 17.67 seconds
Started Jun 26 06:58:40 PM PDT 24
Finished Jun 26 06:58:59 PM PDT 24
Peak memory 205560 kb
Host smart-3f326996-f50a-4cb2-8fef-64acad37bad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430143286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2430143286
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1456288308
Short name T201
Test name
Test status
Simulation time 2425669668 ps
CPU time 1.34 seconds
Started Jun 26 06:58:33 PM PDT 24
Finished Jun 26 06:58:36 PM PDT 24
Peak memory 205352 kb
Host smart-54675e5e-9909-478c-975e-77c8ee8bee93
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456288308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.1456288308
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.871477785
Short name T217
Test name
Test status
Simulation time 2209573442 ps
CPU time 6.95 seconds
Started Jun 26 06:58:28 PM PDT 24
Finished Jun 26 06:58:37 PM PDT 24
Peak memory 205388 kb
Host smart-8d6258ab-6590-4654-b00d-dea1b8027044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871477785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.871477785
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.657805021
Short name T174
Test name
Test status
Simulation time 57155781 ps
CPU time 0.83 seconds
Started Jun 26 06:58:40 PM PDT 24
Finished Jun 26 06:58:42 PM PDT 24
Peak memory 204956 kb
Host smart-b7c4e784-7f4e-478b-b646-230acf04b8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657805021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.657805021
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3897495886
Short name T277
Test name
Test status
Simulation time 1858908822 ps
CPU time 6.12 seconds
Started Jun 26 06:58:38 PM PDT 24
Finished Jun 26 06:58:45 PM PDT 24
Peak memory 205328 kb
Host smart-45dfe3f9-ecd9-415c-a89b-d4562e85cb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897495886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3897495886
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.633450003
Short name T287
Test name
Test status
Simulation time 4678589888 ps
CPU time 5.31 seconds
Started Jun 26 06:58:41 PM PDT 24
Finished Jun 26 06:58:49 PM PDT 24
Peak memory 205396 kb
Host smart-534b647d-322e-4d92-93be-374b4edc68fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633450003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.633450003
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2823748717
Short name T46
Test name
Test status
Simulation time 2529449599 ps
CPU time 2.13 seconds
Started Jun 26 06:58:42 PM PDT 24
Finished Jun 26 06:58:46 PM PDT 24
Peak memory 205492 kb
Host smart-a3077425-614c-46e1-b19f-0d949acb6cba
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823748717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2823748717
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.254621800
Short name T246
Test name
Test status
Simulation time 3262650834 ps
CPU time 10.45 seconds
Started Jun 26 06:58:42 PM PDT 24
Finished Jun 26 06:58:55 PM PDT 24
Peak memory 205360 kb
Host smart-6b8b36c9-fd3d-4a06-92fc-4b18896ac757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254621800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.254621800
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.1147945502
Short name T15
Test name
Test status
Simulation time 8965704445 ps
CPU time 8.95 seconds
Started Jun 26 06:58:40 PM PDT 24
Finished Jun 26 06:58:50 PM PDT 24
Peak memory 213384 kb
Host smart-697c0a5d-aebf-4f69-aa2f-6a77eb334bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147945502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1147945502
Directory /workspace/9.rv_dm_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%