Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	184781	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	553419	1		T2	6		T7	1		T4	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	446263	1		T4	6		T5	13		T25	8
values[0x0]	143343	1		T2	9		T7	1		T4	5
values[0x1]	148594	1		T2	5		T7	4		T4	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	141554	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	596646	1		T2	6		T7	2		T4	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2479	1		T158	1		T71	10		T68	73
valid_sources[0x01]	2927	1		T158	1		T68	44		T93	8
valid_sources[0x02]	2578	1		T6	3		T71	4		T68	61
valid_sources[0x03]	3726	1		T4	1		T159	1		T71	1
valid_sources[0x04]	3101	1		T15	1		T18	1		T71	10
valid_sources[0x05]	3229	1		T56	2		T160	2		T71	3
valid_sources[0x06]	2878	1		T123	2		T71	10		T68	29
valid_sources[0x07]	3048	1		T15	2		T71	6		T68	83
valid_sources[0x08]	3064	1		T50	1		T161	1		T71	5
valid_sources[0x09]	2891	1		T35	1		T146	2		T162	13
valid_sources[0x0a]	2414	1		T51	2		T71	1		T68	37
valid_sources[0x0b]	2459	1		T30	3		T42	22		T50	1
valid_sources[0x0c]	3270	1		T56	1		T35	2		T146	1
valid_sources[0x0d]	2765	1		T163	2		T71	1		T68	57
valid_sources[0x0e]	3048	1		T71	6		T68	32		T69	4
valid_sources[0x0f]	2762	1		T158	2		T68	18		T72	3
valid_sources[0x10]	2807	1		T159	1		T50	1		T68	18
valid_sources[0x11]	4525	1		T158	1		T164	1		T71	4
valid_sources[0x12]	2537	1		T5	4		T15	4		T92	1
valid_sources[0x13]	3171	1		T58	3		T50	1		T51	1
valid_sources[0x14]	2744	1		T4	3		T123	1		T71	4
valid_sources[0x15]	2992	1		T7	1		T50	2		T165	1
valid_sources[0x16]	2708	1		T15	1		T71	7		T68	8
valid_sources[0x17]	3393	1		T35	1		T71	27		T68	54
valid_sources[0x18]	3090	1		T158	1		T50	2		T51	3
valid_sources[0x19]	3513	1		T22	1		T71	4		T68	48
valid_sources[0x1a]	2528	1		T92	1		T146	1		T50	1
valid_sources[0x1b]	2855	1		T50	2		T71	6		T68	38
valid_sources[0x1c]	3089	1		T75	1		T35	1		T146	1
valid_sources[0x1d]	2865	1		T4	2		T50	1		T51	2
valid_sources[0x1e]	2915	1		T164	1		T71	12		T68	32
valid_sources[0x1f]	2392	1		T71	1		T68	44		T69	3
valid_sources[0x20]	2733	1		T56	1		T58	1		T71	3
valid_sources[0x21]	3199	1		T7	1		T50	1		T166	1
valid_sources[0x22]	2408	1		T25	2		T56	1		T50	1
valid_sources[0x23]	2859	1		T8	1		T75	1		T35	1
valid_sources[0x24]	2695	1		T71	3		T68	39		T69	2
valid_sources[0x25]	2679	1		T5	9		T133	1		T146	2
valid_sources[0x26]	2487	1		T35	1		T161	1		T71	1
valid_sources[0x27]	2435	1		T15	1		T71	4		T68	22
valid_sources[0x28]	2840	1		T23	1		T68	26		T69	5
valid_sources[0x29]	3179	1		T167	3		T137	7		T166	2
valid_sources[0x2a]	3166	1		T146	1		T158	1		T50	1
valid_sources[0x2b]	2992	1		T168	1		T161	1		T71	5
valid_sources[0x2c]	2781	1		T75	2		T166	1		T71	1
valid_sources[0x2d]	2699	1		T57	6		T71	2		T68	53
valid_sources[0x2e]	2439	1		T30	2		T146	1		T161	1
valid_sources[0x2f]	2446	1		T6	1		T71	4		T68	19
valid_sources[0x30]	2967	1		T146	3		T71	3		T68	17
valid_sources[0x31]	3129	1		T137	5		T166	2		T68	61
valid_sources[0x32]	2841	1		T56	1		T54	1		T50	3
valid_sources[0x33]	2669	1		T161	1		T71	3		T68	65
valid_sources[0x34]	2459	1		T159	1		T71	4		T68	16
valid_sources[0x35]	3341	1		T25	5		T21	1		T71	2
valid_sources[0x36]	3197	1		T68	44		T69	17		T93	6
valid_sources[0x37]	3186	1		T56	1		T92	1		T71	8
valid_sources[0x38]	2992	1		T71	2		T68	54		T69	4
valid_sources[0x39]	3303	1		T167	8		T55	1		T51	2
valid_sources[0x3a]	2944	1		T2	7		T168	1		T51	3
valid_sources[0x3b]	2927	1		T56	1		T169	1		T50	2
valid_sources[0x3c]	2584	1		T161	1		T71	8		T68	24
valid_sources[0x3d]	3229	1		T50	1		T71	1		T68	34
valid_sources[0x3e]	2913	1		T8	1		T50	3		T164	1
valid_sources[0x3f]	2856	1		T146	1		T71	2		T68	73
valid_sources[0x40]	2738	1		T7	1		T71	1		T68	30
valid_sources[0x41]	2571	1		T15	3		T158	1		T20	1
valid_sources[0x42]	3262	1		T71	10		T68	43		T69	8
valid_sources[0x43]	2997	1		T22	1		T166	1		T51	8
valid_sources[0x44]	3019	1		T146	2		T161	1		T71	1
valid_sources[0x45]	2670	1		T56	1		T170	1		T163	3
valid_sources[0x46]	2894	1		T71	7		T68	3		T69	3
valid_sources[0x47]	2572	1		T6	1		T58	5		T166	2
valid_sources[0x48]	2970	1		T15	1		T71	4		T68	87
valid_sources[0x49]	2389	1		T6	1		T159	1		T137	11
valid_sources[0x4a]	2672	1		T7	1		T15	1		T159	1
valid_sources[0x4b]	3180	1		T159	1		T50	1		T71	7
valid_sources[0x4c]	2589	1		T169	4		T71	4		T68	37
valid_sources[0x4d]	2902	1		T5	19		T92	1		T21	1
valid_sources[0x4e]	3210	1		T159	1		T51	1		T164	1
valid_sources[0x4f]	2917	1		T35	1		T158	1		T51	1
valid_sources[0x50]	3772	1		T6	4		T75	3		T71	4
valid_sources[0x51]	2929	1		T71	15		T68	43		T69	10
valid_sources[0x52]	3308	1		T15	1		T171	1		T50	1
valid_sources[0x53]	2896	1		T50	3		T166	1		T165	2
valid_sources[0x54]	2866	1		T29	1		T71	2		T68	32
valid_sources[0x55]	2978	1		T6	7		T57	1		T169	3
valid_sources[0x56]	3021	1		T146	1		T21	1		T158	2
valid_sources[0x57]	2684	1		T172	1		T137	3		T161	1
valid_sources[0x58]	3020	1		T161	1		T173	5		T174	1
valid_sources[0x59]	3155	1		T158	1		T71	1		T68	47
valid_sources[0x5a]	2989	1		T169	1		T51	2		T68	26
valid_sources[0x5b]	2583	1		T15	1		T75	1		T170	3
valid_sources[0x5c]	2644	1		T11	38		T71	3		T68	32
valid_sources[0x5d]	2463	1		T71	8		T68	19		T69	3
valid_sources[0x5e]	2958	1		T75	4		T161	1		T71	2
valid_sources[0x5f]	2911	1		T159	1		T50	4		T174	1
valid_sources[0x60]	2788	1		T71	16		T68	40		T69	9
valid_sources[0x61]	3110	1		T6	1		T71	8		T68	44
valid_sources[0x62]	3076	1		T21	1		T55	3		T71	4
valid_sources[0x63]	2854	1		T68	62		T72	1		T69	18
valid_sources[0x64]	2599	1		T163	2		T51	1		T68	45
valid_sources[0x65]	3106	1		T5	6		T158	2		T161	1
valid_sources[0x66]	2731	1		T50	1		T71	5		T68	19
valid_sources[0x67]	2514	1		T71	17		T68	39		T69	2
valid_sources[0x68]	2689	1		T71	6		T68	54		T72	4
valid_sources[0x69]	2141	1		T92	2		T159	1		T68	28
valid_sources[0x6a]	2709	1		T25	1		T16	5		T161	1
valid_sources[0x6b]	3531	1		T159	1		T162	6		T55	1
valid_sources[0x6c]	3045	1		T169	1		T55	1		T68	75
valid_sources[0x6d]	3068	1		T6	2		T71	1		T68	41
valid_sources[0x6e]	3281	1		T92	1		T75	3		T71	14
valid_sources[0x6f]	2830	1		T35	1		T22	1		T68	40
valid_sources[0x70]	2705	1		T18	1		T68	17		T69	4
valid_sources[0x71]	3007	1		T22	1		T71	2		T68	45
valid_sources[0x72]	3045	1		T133	3		T146	1		T169	1
valid_sources[0x73]	2558	1		T25	4		T6	1		T35	1
valid_sources[0x74]	3111	1		T14	12		T92	1		T35	1
valid_sources[0x75]	3043	1		T5	12		T92	1		T50	1
valid_sources[0x76]	3172	1		T68	23		T69	6		T93	4
valid_sources[0x77]	2727	1		T6	1		T71	2		T68	31
valid_sources[0x78]	3014	1		T25	1		T35	2		T54	10
valid_sources[0x79]	3186	1		T4	2		T133	6		T161	1
valid_sources[0x7a]	3092	1		T6	2		T167	2		T71	14
valid_sources[0x7b]	2652	1		T21	1		T161	1		T71	10
valid_sources[0x7c]	3388	1		T16	6		T68	49		T72	3
valid_sources[0x7d]	2716	1		T6	1		T175	1		T51	1
valid_sources[0x7e]	2674	1		T35	1		T161	1		T51	1
valid_sources[0x7f]	2458	1		T15	1		T159	1		T50	1
valid_sources[0x80]	2867	1		T172	1		T21	2		T22	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

271022

1

T4

3

T5

9

T25

2

values[0x0]

all_enables

biggest_size

141291

1

T2

5

T4

1

T5

9

values[0x1]

all_enables

biggest_size

141106

1

T2

1

T7

1

T5

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4859	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	21011	1		T1	1		T2	1		T3	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9556	1		T71	6		T68	71		T72	3
values[0x0]	8029	1		T2	1		T3	1		T4	4
values[0x1]	8285	1		T1	1		T3	3		T7	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3664	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	22206	1		T1	1		T2	1		T3	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	837	1		T176	1		T76	1		T69	1
valid_sources[0x01]	287	1		T177	1		T69	2		T96	3
valid_sources[0x02]	117	1		T92	4		T146	3		T69	3
valid_sources[0x03]	98	1		T178	1		T69	1		T84	6
valid_sources[0x04]	71	1		T168	1		T179	1		T22	3
valid_sources[0x05]	91	1		T17	1		T180	18		T181	1
valid_sources[0x06]	83	1		T9	1		T182	1		T183	1
valid_sources[0x07]	191	1		T69	1		T85	1		T96	1
valid_sources[0x08]	83	1		T25	4		T26	1		T28	1
valid_sources[0x09]	52	1		T91	1		T98	5		T101	1
valid_sources[0x0a]	72	1		T184	2		T85	1		T90	2
valid_sources[0x0b]	75	1		T184	1		T185	1		T69	3
valid_sources[0x0c]	101	1		T38	10		T186	1		T55	1
valid_sources[0x0d]	91	1		T69	1		T85	1		T91	1
valid_sources[0x0e]	50	1		T167	1		T85	1		T96	1
valid_sources[0x0f]	78	1		T4	9		T52	1		T28	1
valid_sources[0x10]	79	1		T96	6		T91	2		T98	2
valid_sources[0x11]	70	1		T187	1		T133	10		T167	1
valid_sources[0x12]	101	1		T168	1		T188	1		T162	1
valid_sources[0x13]	99	1		T161	1		T189	3		T85	2
valid_sources[0x14]	65	1		T190	1		T191	3		T192	2
valid_sources[0x15]	106	1		T167	1		T69	1		T87	4
valid_sources[0x16]	76	1		T193	1		T85	1		T96	17
valid_sources[0x17]	155	1		T22	1		T183	3		T69	1
valid_sources[0x18]	54	1		T194	1		T163	3		T98	4
valid_sources[0x19]	85	1		T44	1		T188	1		T159	6
valid_sources[0x1a]	97	1		T181	1		T71	5		T85	1
valid_sources[0x1b]	82	1		T193	1		T195	1		T168	1
valid_sources[0x1c]	56	1		T27	6		T28	1		T69	1
valid_sources[0x1d]	89	1		T15	8		T90	4		T98	4
valid_sources[0x1e]	154	1		T52	1		T188	1		T161	1
valid_sources[0x1f]	103	1		T13	4		T49	1		T68	3
valid_sources[0x20]	87	1		T49	1		T76	1		T196	12
valid_sources[0x21]	206	1		T131	6		T188	1		T54	1
valid_sources[0x22]	132	1		T197	2		T168	1		T17	1
valid_sources[0x23]	63	1		T138	1		T166	1		T69	2
valid_sources[0x24]	85	1		T56	8		T71	1		T85	1
valid_sources[0x25]	53	1		T198	1		T186	1		T90	3
valid_sources[0x26]	88	1		T85	1		T98	1		T99	1
valid_sources[0x27]	100	1		T3	1		T76	2		T199	1
valid_sources[0x28]	86	1		T200	1		T68	3		T69	1
valid_sources[0x29]	51	1		T134	1		T201	1		T162	1
valid_sources[0x2a]	123	1		T198	2		T76	1		T202	9
valid_sources[0x2b]	95	1		T203	1		T87	4		T91	2
valid_sources[0x2c]	64	1		T69	2		T96	3		T97	4
valid_sources[0x2d]	81	1		T5	1		T204	1		T205	1
valid_sources[0x2e]	75	1		T206	1		T134	1		T207	6
valid_sources[0x2f]	96	1		T16	1		T208	1		T84	11
valid_sources[0x30]	83	1		T32	3		T75	2		T69	1
valid_sources[0x31]	78	1		T122	3		T198	1		T160	2
valid_sources[0x32]	207	1		T198	1		T193	1		T183	2
valid_sources[0x33]	52	1		T69	1		T97	2		T98	3
valid_sources[0x34]	109	1		T14	1		T190	1		T186	1
valid_sources[0x35]	137	1		T96	2		T59	13		T101	1
valid_sources[0x36]	368	1		T134	1		T69	1		T96	1
valid_sources[0x37]	80	1		T69	2		T85	1		T90	1
valid_sources[0x38]	104	1		T209	1		T129	6		T137	1
valid_sources[0x39]	71	1		T176	1		T210	1		T69	1
valid_sources[0x3a]	83	1		T23	1		T211	1		T212	1
valid_sources[0x3b]	99	1		T36	1		T37	2		T21	1
valid_sources[0x3c]	191	1		T14	1		T213	2		T128	1
valid_sources[0x3d]	74	1		T89	3		T85	1		T90	4
valid_sources[0x3e]	100	1		T43	1		T214	1		T93	2
valid_sources[0x3f]	97	1		T6	7		T188	1		T186	1
valid_sources[0x40]	52	1		T215	4		T69	1		T90	2
valid_sources[0x41]	101	1		T216	1		T217	1		T218	7
valid_sources[0x42]	58	1		T30	1		T213	1		T17	1
valid_sources[0x43]	92	1		T167	1		T161	1		T166	1
valid_sources[0x44]	39	1		T96	2		T91	1		T98	3
valid_sources[0x45]	56	1		T31	1		T14	1		T90	1
valid_sources[0x46]	112	1		T39	3		T136	1		T184	1
valid_sources[0x47]	76	1		T219	1		T69	2		T85	1
valid_sources[0x48]	87	1		T57	1		T78	6		T186	1
valid_sources[0x49]	70	1		T176	1		T148	1		T217	1
valid_sources[0x4a]	96	1		T193	1		T166	1		T96	1
valid_sources[0x4b]	86	1		T3	1		T8	1		T69	3
valid_sources[0x4c]	90	1		T183	1		T212	1		T98	2
valid_sources[0x4d]	59	1		T5	2		T24	5		T142	1
valid_sources[0x4e]	67	1		T204	1		T203	1		T137	1
valid_sources[0x4f]	95	1		T193	2		T69	1		T85	2
valid_sources[0x50]	59	1		T220	1		T85	1		T91	1
valid_sources[0x51]	88	1		T206	1		T202	1		T72	1
valid_sources[0x52]	454	1		T221	1		T187	1		T222	1
valid_sources[0x53]	57	1		T2	1		T221	1		T188	1
valid_sources[0x54]	124	1		T23	1		T69	1		T90	2
valid_sources[0x55]	51	1		T52	1		T69	1		T85	1
valid_sources[0x56]	86	1		T223	1		T176	1		T77	4
valid_sources[0x57]	75	1		T181	1		T68	3		T69	1
valid_sources[0x58]	90	1		T176	1		T224	1		T137	1
valid_sources[0x59]	70	1		T225	1		T69	1		T85	1
valid_sources[0x5a]	165	1		T63	2		T77	1		T17	1
valid_sources[0x5b]	52	1		T219	1		T189	1		T90	4
valid_sources[0x5c]	95	1		T183	1		T217	1		T90	1
valid_sources[0x5d]	139	1		T49	1		T17	1		T186	1
valid_sources[0x5e]	81	1		T28	1		T21	1		T69	2
valid_sources[0x5f]	100	1		T198	1		T221	1		T169	6
valid_sources[0x60]	170	1		T178	1		T90	3		T96	8
valid_sources[0x61]	78	1		T63	8		T222	1		T69	2
valid_sources[0x62]	58	1		T147	2		T226	1		T141	1
valid_sources[0x63]	65	1		T147	1		T98	4		T59	1
valid_sources[0x64]	61	1		T39	1		T85	1		T87	2
valid_sources[0x65]	136	1		T181	1		T227	1		T161	1
valid_sources[0x66]	82	1		T197	1		T166	1		T96	3
valid_sources[0x67]	79	1		T212	6		T69	3		T96	4
valid_sources[0x68]	69	1		T132	1		T163	1		T87	5
valid_sources[0x69]	74	1		T123	1		T204	1		T147	1
valid_sources[0x6a]	82	1		T93	1		T90	5		T96	2
valid_sources[0x6b]	114	1		T198	1		T77	3		T69	1
valid_sources[0x6c]	117	1		T49	1		T69	2		T85	2
valid_sources[0x6d]	51	1		T84	6		T85	1		T98	3
valid_sources[0x6e]	175	1		T5	1		T206	1		T146	6
valid_sources[0x6f]	113	1		T162	1		T85	1		T96	4
valid_sources[0x70]	76	1		T198	2		T228	3		T69	1
valid_sources[0x71]	75	1		T229	1		T168	1		T69	1
valid_sources[0x72]	77	1		T193	1		T17	1		T230	2
valid_sources[0x73]	139	1		T193	1		T69	1		T85	1
valid_sources[0x74]	145	1		T69	3		T84	16		T85	1
valid_sources[0x75]	100	1		T202	1		T174	1		T69	2
valid_sources[0x76]	104	1		T231	1		T204	1		T90	3
valid_sources[0x77]	57	1		T69	2		T85	1		T107	2
valid_sources[0x78]	108	1		T63	4		T11	8		T232	7
valid_sources[0x79]	79	1		T233	1		T88	9		T69	2
valid_sources[0x7a]	89	1		T78	1		T69	1		T90	2
valid_sources[0x7b]	132	1		T84	7		T85	1		T90	1
valid_sources[0x7c]	81	1		T203	1		T12	8		T188	1
valid_sources[0x7d]	113	1		T75	1		T148	3		T234	1
valid_sources[0x7e]	89	1		T235	2		T48	1		T236	1
valid_sources[0x7f]	84	1		T9	1		T172	1		T85	1
valid_sources[0x80]	58	1		T183	1		T175	1		T68	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6711

1

T71

4

T68

20

T72

1

values[0x0]

all_enables

biggest_size

7227

1

T2

1

T3

1

T4

4

values[0x1]

all_enables

biggest_size

7073

1

T1

1

T3

3

T7

1