SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 764186 | 1 | T2 | 14 | T7 | 5 | T4 | 19 | |||
auto[1] | 20074 | 1 | T50 | 80 | T51 | 80 | T68 | 17 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 784033 | 1 | T2 | 14 | T7 | 5 | T4 | 19 | |||
values[1] | 21 | 1 | T68 | 3 | T101 | 2 | T124 | 1 | |||
values[2] | 2 | 1 | T149 | 1 | T150 | 1 | - | - | |||
values[3] | 121 | 1 | T68 | 4 | T85 | 11 | T86 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 784040 | 1 | T2 | 14 | T7 | 5 | T4 | 19 | |||
values[1] | 25 | 1 | T68 | 2 | T86 | 2 | T101 | 2 | |||
values[2] | 5 | 1 | T101 | 1 | T150 | 1 | T151 | 1 | |||
values[3] | 119 | 1 | T68 | 7 | T85 | 7 | T86 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 783920 | 1 | T2 | 14 | T7 | 5 | T4 | 19 | |||
auto[TlIntgErrCmd] | 120 | 1 | T68 | 5 | T85 | 8 | T86 | 5 | |||
auto[TlIntgErrData] | 113 | 1 | T68 | 7 | T85 | 5 | T86 | 2 | |||
auto[TlIntgErrBoth] | 107 | 1 | T68 | 8 | T85 | 7 | T86 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 42949 | 0 | T1 | 1 | T2 | 1 | T3 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 42728 | 1 | T1 | 1 | T2 | 1 | T3 | 4 | |||
values[1] | 22 | 1 | T68 | 1 | T85 | 3 | T124 | 2 | |||
values[2] | 7 | 1 | T85 | 1 | T86 | 1 | T127 | 1 | |||
values[3] | 106 | 1 | T68 | 7 | T85 | 8 | T86 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 42716 | 1 | T1 | 1 | T2 | 1 | T3 | 4 | |||
values[1] | 28 | 1 | T68 | 1 | T85 | 4 | T86 | 3 | |||
values[2] | 12 | 1 | T68 | 2 | T85 | 1 | T124 | 2 | |||
values[3] | 111 | 1 | T68 | 3 | T85 | 6 | T86 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 42609 | 1 | T1 | 1 | T2 | 1 | T3 | 4 | |||
auto[TlIntgErrCmd] | 107 | 1 | T68 | 10 | T85 | 5 | T86 | 3 | |||
auto[TlIntgErrData] | 119 | 1 | T68 | 5 | T85 | 7 | T86 | 2 | |||
auto[TlIntgErrBoth] | 114 | 1 | T68 | 5 | T85 | 8 | T86 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |