Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	229049	1		T2	8		T7	4		T4	15
full_word	555211	1		T2	6		T7	1		T4	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	783920	1		T2	14		T7	5		T4	19
auto[TlIntgErrCmd]	120	1		T68	5		T85	8		T86	5
auto[TlIntgErrData]	113	1		T68	7		T85	5		T86	2
auto[TlIntgErrBoth]	107	1		T68	8		T85	7		T86	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	448401	1		T4	6		T5	13		T25	8
auto[1]	335859	1		T2	14		T7	5		T4	13

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	177037	1		T4	3		T5	4		T25	6
auto[TlIntgErrNone]	partial	auto[1]	51696	1		T2	8		T7	4		T4	12
auto[TlIntgErrNone]	full_word	auto[0]	271216	1		T4	3		T5	9		T25	2
auto[TlIntgErrNone]	full_word	auto[1]	283971	1		T2	6		T7	1		T4	1
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T68	2		T85	3		T86	3
auto[TlIntgErrCmd]	partial	auto[1]	71	1		T68	3		T85	5		T86	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T149	1		T152	1		T153	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T124	1		T127	1		T154	1
auto[TlIntgErrData]	partial	auto[0]	56	1		T68	4		T85	3		T86	1
auto[TlIntgErrData]	partial	auto[1]	52	1		T68	2		T85	2		T86	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T152	1		T155	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1		T68	1		T151	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T68	4		T85	5		T86	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T68	4		T85	2		T101	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T124	1		T152	1		T156	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T86	1		T152	1		T150	1