Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	113246610	14399	0	0
late_debug_enable_rd_A	113246610	3698	0	0
late_debug_enable_regwen_rd_A	113246610	2621	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113246610	14399	0	0
T59	172529	703	0	0
T68	108797	3	0	0
T69	82207	52	0	0
T70	80566	49	0	0
T84	103075	59	0	0
T85	183418	4	0	0
T86	211079	1	0	0
T87	12467	148	0	0
T90	233662	66	0	0
T91	13393	116	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113246610	3698	0	0
T69	82207	40	0	0
T85	183418	53	0	0
T87	12467	49	0	0
T95	6408	5	0	0
T96	332486	956	0	0
T97	56209	10	0	0
T98	169444	608	0	0
T106	17015	12	0	0
T124	132094	63	0	0
T125	129529	71	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113246610	2621	0	0
T69	82207	18	0	0
T85	183418	89	0	0
T87	12467	69	0	0
T97	56209	23	0	0
T98	169444	564	0	0
T106	17015	7	0	0
T124	132094	24	0	0
T125	129529	28	0	0
T126	129052	39	0	0
T127	102218	20	0	0